Usability Lab

Solido™ SPICE: Determining the Appropriate RF Analysis Method with DNA Advisor

Evaluate three representative circuits to determine the most effective steady-state analysis approach. Starting from Solido™ Design Environment (DE), run simulations by Solido™ SPICE and leverage the DNA Advisor within Solido™ Waveform Analyzer to automatically assess the results and recommend the best analysis method and parameters.

Symphony Pro: Identifying and Debugging Functional Issues in Mixed-Signal Circuits

Identify and debug functional issues within complex mixed-signal circuits. Gain hands-on experience utilizing the powerful Siemens Symphony Pro for advanced analog mixed-signal (AMS) simulation. You will also explore fault isolation and analysis techniques using the intuitive MS Visualizer environment.

Solido™ Design Environment: Sweeping by Device Types with Solido Cell Optimizer

Explore the new "sweep by device types" functionality in the Cell Optimizer tool. Users will be able to add device types as a parameter for sweeping and order the device types based on the targeted output impact in their optimization runs.

Solido™ PVTMC Verifier: AI-Powered Trimming and Optimization In-the-Loop

Set up a two-stage trimming run in-the-loop with Solido™ PVTMC Verifier and define a multi-testbench flow that automatically determines the correct trim code and optimizes the user-defined target in as few simulations as possible.

Questa™ Developer: Agentic Features for Design Creation and Verification

Explore a new generation of AI-assisted workflows and agentic assistants that help engineers move faster, from writing RTL and testbench code to diagnosing issues and navigating complex design structures. Provide feedback that will shape the next wave of intelligent design and verification workflows.

Questa™ One SFV Lint: Use Automated Analyses to Reduce Debug Efforts

Look at automated analyses that catch common testbench issues, enforce best practices, and reduce downstream debug effort. Participants will work directly in the Questa™ Lint environment, leveraging batch mode, the streamlined Lint UI, and violation review capabilities to explore how these new checks fit into existing flows. Your feedback could shape the next set of checks for linting a testbench.

Catapult™ AI/NN: Even higher-level synthesis, From Python to RTL

Experience our new addition to Catapult: Catapult AI/NN. Dive into the Python scripts that take your model from Python to RTL and explore the impact of Post Training Quantization vs Quantized Aware Training on accuracy, area, and training time.

Calibre® RVE™: Check Assist, User Notes, and AI Chatbot

Explore new productivity and AI tools for use with Calibre® RVE: Check Assist, and Chatbot, which help designers understand and debug DRC checks.

Calibre® AI Run Advisor: Intelligent Configuration & Real-Time Monitoring

Experience Advisor’s AI-driven Calibre® nmDRC setup recommendations and real-time visibility into system and job-level metrics. The Live Run Monitor and Post-Run Report capabilities help identify bottlenecks, simplify debugging, and optimize Calibre® nmDRC runs for better performance in both batch and Calibre® Interactive™ flows.

Calibre® Vision AI: Faster Full-Chip DRC Debugging Through Signal Analysis and the FUSE Documentation Chatbot

Explore signal analysis and FUSE chatbot prompting in Calibre® Vision AI for faster DRC debugging.

Insight Analyzer: GUI Features to Simplify Project Setup

Insight Analyzer is part of the Calibre® family, complementing Calibre® PERC reliability flows, with a focus on finding transistor leakage and floating gates very early in the design process. Explore recent enhancements to the Insight Analyzer GUI that simplify advanced project setup.

Shift-Left Antenna Flows: Debug, Selection, and Short Isolation

Simplify and accelerate the debugging of antenna violations in advanced nodes using Calibre®'s powerful analysis flows.

Calibre® xACT™ Digital /pex_stats: An Overview of LEF/DEF Signoff Extraction Flow and Netlist Correlation/Analysis

Discover powerful tools to streamline your digital extraction flow and to optimize the downstream netlist analysis and comparison. Assemble and analyze a complete digital extraction flow in just a few minutes!

mPower™ Digital: Vector-Based Dynamic EM/IR Analysis

Explore two key workflows for digital EM/IR signoff: vector-based dynamic IR drop analysis and electromigration (EM) analysis. Gain practical experience in identifying dynamic IR drop hotspots, as well as pinpointing power/ground (PG) and signal EM violations, by interpreting analysis results through the mPower Digital tool's GUI maps and detailed text reports.

PowerPro®: Guided Power Optimization and Power Estimation for Today’s Power-Sensitive Designs

Experiment with PowerPro power optimization techniques to reduce power at various RTL stages. Perform fine-grained sequential clock gating to get power-optimized and energy-efficient RTL. Using the Tcl command shell and GUI, you will go through the guided power optimization flow and view the guidance reports.

Aprisa™ AI: Interactively Analyze and Optimize Your Digital Design in Natural Language

Use generative AI capabilities in Aprisa™ AI to analyze and optimize a design in real-time using natural language. Experience how interacting with Aprisa™ AI through prompts, boosts productivity by accelerating tool ramp-up and significantly reduces overall design implementation turnaround time.

Aprisa™ RTL: Cross-Probing to Analyze and Debug Your Digital Design

This lab leverages Aprisa™ 's cross-probing feature to identify connections between RTL, schematic, and layout views. Explore how to effectively use the cross-probing functionality to debug critical paths and other design-related issues such as congestion.

Tessent™ AnalogTest: Automatically Generate Mixed-Signal Circuit Tests

Tessent™ AnalogTest delivers a revolutionary change from traditional spec-based testing of AMS ICs to block-oriented and structural testing. Using digital IJTAG access, ATPG and defect-oriented test, it simplifies test generation, improves defect coverage, and reduces both test time and costs. This lab demonstrates the workflow through an intuitive interface and showcases the tool’s capabilities for optimized DFT implementation with minimal performance impact.

Tessent™ Visualizer: Quickly Identify and Improve Complex RTL

Complex RTL is difficult to edit and maintain and poses significant testability challenges. Discover how the Tessent™ Visualizer RTL Metrics Browser can help you identify problematic or complex RTL early in your design process. Learn how to increase test point efficiency and highlight and restructure RTL regions to improve testability. Optimize your RTL design workflow with Tessent™ Visualizer!

Tessent™ LFSR Mode: Testing Segments of the SSN Bus Not Used During Wafer Probe

The in-system test controller hardware is typically not used during wafer probe tests, which leaves some SSN segments untested. Discover how to use Tessent™ LFSR to create patterns that test these segments during wafer probe testing.

Tessent™ Chatbot: Fuse-Based AI Chatbot for Guidance

Explore Tessent™ Fuse-based AI chatbot integration by using question-and-answer style prompts. Experience how the new Fuse-based AI chatbot can answer questions about DFT methodology and Tessent™ software usage.