Usability Lab

Explore the Aprisa Cross-Probing feature for design flow

This lab covers the basic workflow of leveraging the Aprisa Cross-Probing feature to identify connections between register level transfer, schematic and layout views. The aim is to provide designers with a practical understanding of how to effectively use the Cross-Probing functionality to debug critical paths and other design-related issues, such as congestion.

Calibre RealTime

Run Calibre nmDRC Recon from PnR environment using Calibre RealTime Digital

In this lab, you will use Calibre RealTime Digital to run design rule checking (DRC) recon on different regions of a design. Calibre RealTime Digital is an interface that can be integrated with different PNR/design tools, and it lets you run quality DRC checks early in the flow during the physical design phase. In this lab, we will use the Siemens Aprisa system-on-chip (SoC) design software as a place-and-route (PnR) environment to run Calibre nmDRC in recon mode. Calibre nmDRC recon technology reduces iteration and debug time by minimizing the rules and data required for DRC in early design iterations.

Insight Analyzer

Insight multi-feature lab

With a focus on finding transistor leakage and floating gates early in the design process, Insight Analyzer features an easy-to-use interface. In this lab, you will set up and run a project, then explore the results using the new Insight Visualizer feature, which draws each circuit violation as an annotated schematic, making it easy to understand a complex result. Insight Analyzer is part of the Calibre family, complementing Calibre PERC reliability flows much earlier in the custom digital and analog design flows.

Calibre nmDRC

Calibre nmDRC shift-left antenna analysis flows

In this lab, you will learn how to easily debug complex antenna violations using the Calibre antenna analysis flows. Debugging antenna violations in advanced nodes is a complex and time-consuming task. You will utilize the Calibre antenna analysis flows with two sets of capabilities to simplify and accelerate this process.

Calibre Interactive/RVE

Artifical-intelligence-based run advisor in Calibre Interactive

This lab introduces a new run advisor that uses artificial intelligence to simplify Calibre setup and improve job performance and hardware utilization. The run advisor analyzes a Calibre DRC run and generates a report that gives the user recommendations on how they can improve the setup and hardware configuration for the next run. It also includes live job monitoring so users can easily track the progress of their Calibre job and quickly identify issues, like swap memory, in real time.

Calibre Interactive RVE

Advanced settings in multiple job submission GUI

This lab presents new productivity-focused enhancements in the Calibre interactive multiple job submission graphical user interface, including a global settings mode for managing multiple jobs on a single design, support for custom pages and options, time-based job scheduling and various other improvements.

Calibre DESIGNrev

Utilize perpendicular rulers in Calibre DESIGNrev to accelerate Calibre nmDRC debug

Accelerate Calibre nmDRC debug on advanced nodes using the new perpendicular ruler mode in Calibre DESIGNrev.

Calibre pattern matching

Interactive symmetry (smarter check)

Extent-based symmetry checking can lead to many false violations. The smart checking option in the interactive symmetry solution works by identifying the true center of symmetry for a specific shape.

Calibre parasitic extraction

Optimize the performance of parasitic extraction runs in advanced nodes with Calibre xACT multi-corner flow

Set up Calibre xACT to perform simultaneous multi-corner extraction for advanced nodes, extracting all of the desired processes, multi-patterning and temperature corners in a single run.

Calibre parasitic extraction

Unlock the power of parasitic component analysis with Calibre RVE

Use Calibre RVE to analyze how parasitics are affecting your design response. You can highlight parasitic resistance and capacitance by layer, do point-to-point resistance and inductance calculations and show resistance heatmaps to identify problematic areas.

Catapult AI/NN: even higher-level synthesis, from Python to RTL

Experience our new addition to Catapult: Catapult AI/NN. In this session, we will dive into the Python scripts that take your model from Python to RTL. We will explore precision by looking at the impact of post-training quantization vs quantization-aware training on accuracy, area and training time.

Bridging the gap between functional verification and fault simulation

In this lab, you will learn how to set up fault simulation using Questa Fault Simulator using your existing functional verification tests and how to quickly get to the desired coverage during a fault campaign on automotive chips.

Guided power optimization and power estimation for today's power-sensitive designs

In this lab, you will experiment with the PowerPro power optimization techniques to help reduce power at various RTL stages. Perform fine-grained sequential clock gating to get significantly power-optimized and energy-efficient RTL. Using the Tool Command Language (TCL) command shell and graphical user interface (GUI), you will load a design-and-go through the guided power optimization flow and view the guidance reports.

How to set up a Corner Group in the Solido Design Environment

This lab introduces the Corner Group capability in the AI-powered Solido Design Environment, a unique and productive way to set up multiple independent corners and group them together for more actions in fewer clicks. Users of analog and mixed-signal design backgrounds are a good fit for this lab.

Identify RTL complexity faster with Tessent Visualizer

Complex RTL is difficult to edit and maintain and poses testability challenges. Discover how the new RTL Metrics Browser can help you identify such problematic or complex RTL early in the design process. Learn how test point efficiency can be increased and how you can highlight and restructure RTL regions to improve testability. Optimize your RTL design workflow with Tessent Visualizer.

Create and debug IJTAG Network with Tessent Visualizer

Learn to use Tessent Visualizer as you create, visualize, and debug the IJTAG network for your design. Debug specification issues. Extract Instrument Connectivity Language (ICL). Explore the Internal JTAG network with built-in introspection features, such as schematic browsing, tracing and expanding a Segment Insertion Bit (SIB) tree.

Achieve faster test coverage analysis with Tessent Visualizer

Explore how Tessent Visualizer can enhance your test coverage analysis process. Learn to navigate your design, analyze data, identify design rule check violations and pinpoint the root cause of test coverage issues.