Technical tracks

Die-die interaction and complex stacking configurations necessitate novel approaches to thermal-mechanical modeling and physical verification. Microsoft, Intel, and ST Microelectronics will present solutions to these challenges.

Optimize performance, power and area with correct-by-construction implementation from physical-aware synthesis to post-route, with less iterations and tight correlation with signoff engines for rapid convergence to design closure.

Explore how expanding Calibre into Implementation, using Calibre cloud computing, and adopting our new AI-assisted debug methodologies improve your workflow by enhancing collaboration and shortening your turnaround time.

Learn how customers leverage Solido's AI-powered design, simulation, library characterization and IP validation solutions to optimize quality, improve productivity and accelerate time-to-market.

Learn how Questa users automate simulation and formal verification, regressions, debug and coverage closure of complex SoCs and FPGAs, dramatically increasing productivity and managing resources more efficiently.

Veloce hardware-assisted verification platforms for emulation, enterprise prototyping and software prototyping allow users to use a shift-left strategy to accelerate system-on-chip (SoC) software, system design and verification.

Use high-level synthesis and verification to design fast, efficient hardware accelerators. Optimize performance, power and area early, with power analysis and signoff ensuring accurate power projection and final IR drop checks.

Create an infrastructure that makes designs more testable to improve quality across the silicon lifecycle. Achieve high-quality test, identify defects/hidden yield limiters and move beyond test to system debug and validation.