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User2User Europe 2026
Usability Lab
Usability labs are interactive, customer-driven user studies designed to answer specific usability questions. Participants complete focused tasks using real tools while product teams observe, learn, and collect actionable feedback.
Usability Lab
Visit the Usability Lab in the atrium from 8:00 a.m. to 5:00 p.m., the lab offers hands‑on access to Siemens EDA tools and experts to explore workflows and provide feedback.
See available labs below.
Solido™ Design Environment: Sweeping by device types with Solido Cell Optimizer
Explore the new "sweep by device types" functionality in the Cell Optimizer tool. Users will be able to add device types as a parameter for sweeping and order the device types based on the targeted output impact in their optimization runs.
Solido™ PVTMC Verifier: AI-Powered trimming and optimization in-the-loop
Set up a two-stage trimming run in-the-loop with Solido™ PVTMC Verifier and define a multi-testbench flow that automatically determines the correct trim code and optimizes the user-defined target in as few simulations as possible.
Solido™ SPICE: Determining the appropriate RF analysis method with DNA Advisor
Evaluate three representative circuits to determine the most effective steady-state analysis approach. Starting from Solido™ Design Environment (DE), run simulations by Solido™ SPICE and leverage the DNA Advisor within Solido™ Waveform Analyzer to automatically assess the results and recommend the best analysis method and parameters.
Symphony Pro: Identifying and debugging functional issues in mixed-signal circuits
Identify and debug functional issues within complex mixed-signal circuits. Gain hands-on experience utilizing the powerful Siemens Symphony Pro for advanced analog mixed-signal (AMS) simulation. You will also explore fault isolation and analysis techniques using the intuitive MS Visualizer environment.
Questa™ Developer: Agentic features for design creation and verification
Explore a new generation of AI-assisted workflows and agentic assistants that help engineers move faster, from writing RTL and testbench code to diagnosing issues and navigating complex design structures. Provide feedback that will shape the next wave of intelligent design and verification workflows.
Calibre® RVE™: Check Assist, User Notes, and AI Chatbot
Explore new productivity and AI tools for use with Calibre® RVE: Check Assist, and Chatbot, which help designers understand and debug DRC checks.
Calibre® Vision AI: Faster full-chip DRC debugging through signal analysis and the FUSE documentation chatbot
Explore signal analysis and FUSE chatbot prompting in Calibre® Vision AI for faster DRC debugging.
Calibre® xACT™ Digital /pex_stats: An Overview of LEF/DEF signoff extraction flow and netlist correlation/analysis
Discover powerful tools to streamline your digital extraction flow and to optimize the downstream netlist analysis and comparison. Assemble and analyze a complete digital extraction flow in just a few minutes!
Aprisa™ RTL: Cross-Probing to analyze and debug your digital design
This lab leverages Aprisa™'s cross-probing feature to identify connections between RTL, schematic, and layout views. Explore how to effectively use the cross-probing functionality to debug critical paths and other design-related issues such as congestion.
Tessent™ AnalogTest: Automatically generate mixed-signal circuit tests
Tessent™ AnalogTest delivers a revolutionary change from traditional spec-based testing of AMS ICs to block-oriented and structural testing. Using digital IJTAG access, ATPG and defect-oriented test, it simplifies test generation, improves defect coverage, and reduces both test time and costs. This lab demonstrates the workflow through an intuitive interface and showcases the tool’s capabilities for optimized DFT implementation with minimal performance impact.
Tessent™ Visualizer: Quickly identify and improve complex RTL
Complex RTL is difficult to edit and maintain and poses significant testability challenges. Discover how the Tessent™ Visualizer RTL Metrics Browser can help you identify problematic or complex RTL early in your design process. Learn how to increase test point efficiency and highlight and restructure RTL regions to improve testability. Optimize your RTL design workflow with Tessent™ Visualizer!
Tessent™ Chatbot: Fuse-Based AI chatbot for guidance
Explore Tessent™ Fuse-based AI chatbot integration by using question-and-answer style prompts. Experience how the new Fuse-based AI chatbot can answer questions about DFT methodology and Tessent™ software usage.