User2User content library

Electric vehicle chips require high-voltage reliability and safety. Infineon uses shunt sensing for battery monitoring, and Aprisa enables efficient placement and routing, which optimizes safety logic and reducing costs.

Register transfer level to graphic design system flows need high-performance computing. Amazon Web Services and Siemens help Aprisa users scale effectively in the cloud, optimizing workflows and computing resources.

Samsung Foundry and Aprisa collaborate on certified tools for efficient, high-performance, low-power designs. This presentation covers tech updates, advanced node challenges, QEDA certification and case studies.

Codasip partners with Siemens for RISC-V processor implementation, utilizing RTL-to-GDSII flow to achieve consistent power, performance and area targets. Partnership delivers reliable virtual tapeout results for customizable IP.

Rivos Inc. & Tsavorite Scalable Intelligence share experiences using Calibre verification tools in the cloud. Learn about Siemens-Managed & Customer-Managed cloud solutions, scaling compute & maintaining designer productivity.

PPA efficiency drives digital designs to smaller nodes. Many turn to 3D ICs to scale. ESD verification remains a challenge needing innovation. Marvell shares their experience with Calibre 3DPERC in their scaling journey.

Calibre PERC's VDR checking combined with SmartFill tools ensures metal fill shapes meet voltage and density requirements, preventing TDDB failures and streamlining VDR verification-tiling generation process.

Calibre 3DThermal enables thermal management in CMOS IC power amplifier design, providing analysis from design to post-silicon. It delivers thermal distribution insights with simulation results matching die measurements.

mPower flow optimizes power integrity through EM and IR-Drop analysis. By incorporating global temperature and self-heating effects, it provides accurate EM checks, enabling robust circuit design with flexibility.

STMicroelectronics PDK transitions from Tcl to JavaScript interface in Calibre Interactive, maintaining customization flexibility. Testing ensures functionality meets user expectations for DRC, Antenna, and Fill GUI features.

STMicroelectronics' DFM Checker uses Calibre YieldAnalyzer and YieldEnhancer to improve layout robustness. Integration with Calibre Auto-Waivers enables efficient waiver management and DFM score tracking for BCD technologies.

Calibre YieldEnhancer SmartFill with eqDRC creates fill shapes meeting strict STI etch, polish, and ILD density requirements. Calibre RTC enables real-time visualization of tiling results within Virtuoso before sign-off.

Building on previous Calibre PERC automation for HBM verification, this approach identifies and fortifies weak links in ESD protection paths. It detects premature triggering risks in parallel paths to prevent device damage.

Calibre PERC Packaged Check automates voltage assignment for mixed-voltage designs, addressing increasing voltage-dependent DRC rules in smaller nodes. Tool propagates voltages and verifies assignments, reducing manual effort.

Discover how AMS-Osram uses Calibre RealTime to perform fast, interactive symmetry checks directly in Virtuoso—accelerating analog layout verification while reducing dependency on traditional batch flows.

Learn about AMD's experiences with Calibre’s new chip-level analysis engine, replacing ASCII-based debugging. AI/ML clustering speeds up DRC analysis, helping engineers triage violations efficiently with guided insights.

ST integrates Calibre 3DStress to analyze mechanical stress impacts during IC fabrication. Tool generates stress maps for electrical simulation, handles multi-die PCB analysis, and features ST's interface for efficient workflow.

For PDK development, Samsung Foundry used Solido LibSPICE and simulation artificial intelligence for batch verification and high-sigma yield analysis, achieving a 6.5x-10x speedup, saving months in cell verification.

We compare brute-force sampling and AI-powered verification. Solido PVTMC Verifier cut simulations 4x, sped time-to-market 12x and identified a rare outlier pre-silicon, showcasing AI's efficiency in semiconductor design.

In the development of memory compiler libraries, accurate timing, power analysis and verification are essential for successful tape out, and for this, accurately characterized Liberty values are needed.

AI-powered quality assurance ensures format consistency and optimizes .lib production. The Solido Validation and Characterization Suite enhances efficiency, reduce iterations and improves quality.

Infineon uses Solido Intellectual Property Validation Suite to verify consistency across design views (Verilog, Liberty, software-defined facility, library exchange format, design exchange format) in automotive chips.

NXP qualifies Solido Design Environment for automotive IC design using PVTMC and high-sigma verifiers. Statistical flows enable robust analog IP verification to meet six-sigma yield requirements across process corners.

Solido DE with PVTMC Verifier optimizes system-on-chip analog block trimming, particularly in non-volatile memory intellectual property, and achieves 7x simulation speedup vs. traditional Monte Carlo.

Lotus Microsystems uses Solido Simulation Suite to optimize power converter design, efficiently handling complex parasitic elements and dynamic switching behavior while maintaining precision and reducing simulation time.

eNVM IP verification flow combines Symphony Pro, Eldo Premier and Symphony Solido FastSPICE for PCM/eSTM technologies. The automated system manages data, testing and debugging, supporting mixed-level simulation models.

Solido Design Environment demonstrates five-sigma process, voltage, temperature, manufacturing, and corn (PVTMC) analysis capabilities.

Solido Design Environment enables robust trimming simulations for high-precision circuit validation, offering advanced analysis and visualization capabilities for post-silicon prediction.

Siemens Defectsim enhances analog coverage for circuit reliability and performance. This case study demonstrates early defect detection and resolution, improving quality in automotive and consumer electronics applications.

Solido Analytics validates memory library files in early process design kits, managing multiple intellectual property releases and detecting issues. Early error detection reduces integration risks.

AI technology speeds up Liberty file creation for missing process, voltage, and temperature combinations in intellectual property libraries, combining fast production with quality analysis and timing verification.

Questa QCX accelerates coverage closure using AI analytics and high-performance engines. Features Bug Hunting, Distributed UCDB, Unreachability Analysis, and ML test selection to optimize verification resources.

P2S methodology converts design parameters to signals for single-pass formal verification of multiple configurations. Custom compiler and Questa Formal achieve 312% runtime reduction vs traditional approaches.

Novel CDC methodology validates fast-to-slow clock domain crossings in SoC designs. Questa CDC enables comprehensive analysis of high-to-low frequency transitions, improving QoR and reducing silicon risks.

Functional verification of L2 cache coherent system leverages Avery CHI VIP to validate memory coherency, protocol compliance, and system-level interactions. Testing ensures robust cache operations and data consistency.

IP development enhanced through UVM framework adoption and Questa CDC verification. Case study details transition from VHDL testbenches, custom CDC scheme implementation, and practical insights from automated checking.

Questa One DFT and Tessent combine in QDX platform to accelerate DFT verification for complex AI chips. Platform reduces simulation time from weeks to hours, optimizing SSN and non-SSN Tessent implementations.

Questa AutoCheck enables 'shift left' verification through automated formal analysis, detecting RTL bugs without testbenches. Visualizer integration simplifies debug workflow, improving productivity by finding issues early.

Intuitive adopts Visualizer for debugging complex surgical robotics systems; addresses challenges of diverse FPGA designs, code reuse, and strict verification needs across processing, video, communications, and control domains.

In this session, you will learn how Tsavorite Scalable Intelligence harnessed the UVM Framework to automate testbench and make-file infrastructure generation and got them started quickly with QuestaSim regressions.

Arm uses Veloce Strato CS to verify CSS and ensure SoC integration quality. Approach optimizes software and performance metrics while reducing development risks for Arm CSS users.

Early adoption of Veloce emulation enhances verification from RTL to gate level, enabling DFT pattern validation and SW bring-up. Strategy accelerates pre-silicon testing and improves first-silicon success rates.

MaxLinear achieves first-silicon success using Veloce emulation for system validation, ensuring pre-silicon firmware readiness.

Veloce Ecosystem enables comprehensive hardware-assisted verification through emulation, prototyping, and hybrid solutions. Platform supports simulation acceleration, SW validation, power analysis, and cloud-based verification.

Ericsson uses Veloce proFPGA and VPS for rapid system architecture prototyping, achieving 40 MHz frequency in four months. Approach enables quick design validation, performance analysis, and early SW development.

Framework leverages Veloce Strato+/CS and proFPGA platforms with VirtuaLAB/VTL interfaces. Automated workflow manages RTL filelist generation, database compilation, and nightly regression testing via web interface.

SiPearl leverages Veloce hybrid emulation for HPC CPU validation, enabling comprehensive BIOS and Linux boot testing. Ecosystem supports software-enabled validation methodology for hardware-software co-development.

Case study demonstrates Veloce cloud platform's role in AI SoC verification, featuring C test creation, CPU trace debugging, CI builds, and platform selection strategies for successful tapeout.

Custom libraries enhance C++ HLS capabilities, improving hardware simulation, debugging, and RTL integration to overcome common hardware design challenges.

Early RTL power analysis enhanced by integrating SPEF data into PowerPro, improving correlation with post-layout estimates. Methodology provides accurate power predictions for ARM IP, enabling better design optimization.

Unified flow integrates standard cell characterization with EM/IR analysis using Solido and mPower tools. Automated approach ensures accuracy, eliminates manual errors, and streamlines reliability verification.

CatapultC enables railway fiber optic axle counter development, transforming Python floating-point algorithms to fixed-point C++ and optimized RTL. Process includes design exploration and verification.

Early-stage power estimation balances accuracy with runtime efficiency. SDF-annotated simulations provide precision but limit analysis windows. Solution needed for faster power analysis earlier in design cycle.

SystemC and SystemC AMS integration enables high-level mixed-signal system validation. HLS methodology streamlines digital implementation while maintaining analog/digital interactions, accelerating design verification.

HLS enables sophisticated in-sensor processing, transforming raw data into meaningful insights locally. Case study demonstrates medical sensor design flow where signal quality analysis enhances system integration.

MBSE and HLS enable flexible HW/SW co-architecting methodology for complex algorithms. Framework supports early system analysis, function partitioning, and continuous verification before hardware completion.

Unified flow combines Solido characterization with mPower EM/IR analysis for standard cells. Automated approach ensures accuracy, eliminates manual errors, and streamlines reliability verification.

Paitron integrates with Xpedition to automate PCB safety analysis, reducing analysis time by 90%. Tool provides model-based failure analysis, safety KPIs, and automated reporting for standards compliance.

BSH leverages EDM and Teamcenter for electronics development, demonstrating system integration and database automation. Highlights importance of collaboration in complex projects through washing machine design example.

Study optimizes mesh and fullwave solver parameters for accurate via stub interference analysis in high-speed digital channels, validating results through simulation-to-measurement correlation.

Explore untapped Xpedition features and AI integration for enhanced engineering productivity. Including automated workflows, design reuse, and practical AI implementation while maintaining data security.

Sintecs demonstrates AI/ML applications in Xpedition and HyperLynx for early flaw detection, performance optimization, and workflow automation, reducing design time and costs.

Using HyperLynx tools for validating complex satellite interfaces (optical, LIDAR, SAR) pre-build. Ensures performance across high-bandwidth connections, flexible PCBs, and matched-impedance connectors.

HyperLynx Schematic Analysis automates circuit checks, identifying voltage issues, missing pull-ups, and component errors. Tool reduces manual review time, enabling focus on complex design tasks.

Unified flow combines Solido characterization with mPower EM/IR analysis for standard cells. Automated approach ensures accuracy, eliminates manual errors, and streamlines reliability verification.

Tessent In-System Test enables AI device testing via APB architecture, detecting silent data corruption without extra BIST hardware. ISTC delivers IS-EDT patterns through SSN for core testing during operation.

Tessent quick synthesis enables early RTL verification post-DFT insertion, detecting issues like broken connections and misconfigurations within hours instead of days. Approach shifts testing left in design cycle.

Framework addresses debugging challenges in complex RISC-V AI accelerators, providing scalable solutions for heterogeneous systems to enhance development efficiency.

Study evaluates OCC insertion methods using symmetric and asymmetric scan channel configurations. Analysis compares test coverage and DFT area impacts across various OCC placements.

Automotive radar design implements new architecture for IST Controller testing via ATE, enabling functional mode validation with LBIST patterns through JTAG/IJTAG topology and NOC access.

Custom implementation integrates Tessent MemoryBIST (MBIST) with secured interface, replacing standard JTAG to enhance security. Solution uses in-house MBIST bridge for connection while maintaining testability.

Integration of Tessent SiliconInsight with NI PXI creates cost-effective debug platform. System combines advanced validation capabilities with precise timing for efficient silicon testing.

DFT standards like IJTAG and IEEE 1838 enable security features for chiplet-based designs. Framework supports authentication and secure communication across chiplets, independent of interconnect technology.