User2User content library

User2User: This presentation will cover the digital implementation development and tapeout of an automotive chip at OnSemi using Aprisa, focusing on ECO from RTL.

Maxlinear shares their study on AMP, Aprisa’s AI-driven Auto Macro Placement applied on their designs, and how the results and runtime compare to their current methodology of hand-placing the macros.

Samsung Foundry unveils a cutting-edge methodology for 3D IC connectivity verification using the Calibre 3DStack tool.

Microsoft Azure Silicon reduced their time to tapeout by scaling Calibre in the cloud. Results that would have taken days were achieved in hours.

NXP describes their advanced cloud architecture optimized for EDA workloads, particularly Calibre physical verification flows including nmDRC, nmLVS and PERC.

Marvell Semiconductor, Inc. discusses using a Calibre shift-left methodology to accelerate physical verification closure for large designs.

Intel describes their methodology for accelerating electrostatic discharge (ESD) verification on IP designs with Calibre PERC.

Learn how to improve productivity using Calibre Yield Server, specifically for post layout flows.

Run EM analysis on custom inductors using mPower Analog. Minor modifications to the regular flow, no need for dedicated layouts. Early analysis in design cycle, full debugging support.

Learn how the new Calibre Interactive GUI is used at ams/OSRAM and its pros and cons for layout and CAD developers.

Industry's first ML for DFM verification leverages Calibre. Identifies metal-via weak points with 20% accuracy boost, reducing false positives, aiding design fixes, and shortening cycle time.

Intel collaborates with SEDA to enhance compute efficiency for complex Calibre PERC runs. Challenges include tight time windows and increasing interface numbers in chip designs.

Lean how Elmos validates chip designs flawlessly with updated DRC/LVS scripts. Calibre-based sign-off ensures comprehensive data collection for reliable tapeout.

Learn how Calibre tools streamline chipfinishing in batch mode, ensuring thorough extraction and reporting for Tape-Out processes. Covers database management, assembly, packaging, and more in semiconductor manufacturing.

Waiver flows filter checks deemed waivable by the foundry or designer. Our PERC LDL flow requires a dedicated waiver flow. This presentation covers its use and our custom PERC GUI.

In submicron ULSI ICs, thermal expansion mismatches between silicon and packaging cause stress and damage. Metal slotting and Calibre Equation-based DRC and DFM functionalities manage these stresses, improving chip reliability.

Electrostatic discharge (ESD) protection design is complex and often manual. Calibre PERC automates verification, reducing errors and man-hours and ensuring robust ESD paths meet HBM requirements.

Balancing timing, performance, power efficiency and budgets in an image sensor design often neglects IR drop analysis, which can impact sensor quality. The mPower power analysis tool ensures consistent power delivery.

Learn how NVIDIA leveraged Solido Additive Learning technology to speed up standard cell library verification with Solido Design Environment while maintaining accuracy on verifying a new process design kit (PDK) revision.

Learn how Allegro MicroSystems leveraged AI-powered Solido Design Environment and Analog FastSPICE to accelerate power management integrated circuit verification, resulting in an overall reduction in verification time.

Learn how SiTime leverages Analog FastSPICE, Symphony and Solido Design Environment ensure seamless integration between the analog and digital components and accelerate verification of high-precision MEMS-based oscillators SoC.

Learn how Microsoft leverages Solido IP Validation to address IP quality issues early in the design process, saving time and money on potential (ECOs), improving overall IP quality in production and integration flows.

Watch this session and learn how to leverage AWS cloud capacity for full cloud migration or peak demand expansion for custom integrated circuit verification workloads, and achieve faster time-to-market.

Learn how Siemens SPICE and mixed-signal simulation tools helped LG achieve significant performance and productivity improvements for phase-locked loop (PLL) intellectual property (IP) versus previous solutions.

Learn how Silicon Creations harnesses Siemens SPICE technology to manage constant growth of design complexity. Highlighting latest performance gains that made 3nm designs possible including simulations results.

Learn how ST uses Solido PVTMC Verifier to predict the dispersion of analog parameters over PVT, and Solido Additive Learning to re-use previous results, reducing the number of runs and accelerating the verification phase.

Learn how Solido Library Profiler and Generator enable users at Infineon to compare and profile .libs coming from different IP sources so optimal dataset can be chosen, leading to better PPA analysis and shorter design cycles.

Learn how ST leveraged Symphony and Visualizer to enhance verification throughput for SmartPower Technologies and analyze and debug the interface between analog and digital in an easier and faster way.

Learn how ST leverages Solido Crosscheck within its IP QA infrastructure to manage IP complexity, providing a comprehensive, proactive IP validation solution to improve the quality of silicon and accelerate SoC delivery.

In this presentation we will share results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: ML provides significant value by improving productivity and accuracy.

In this presentation we dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP in multiple projects.

In this presentation we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process and coverage analysis automation with Questa Verification IQ.

This presentation starts with the introduction of our FPGA-based SoC control system DUT and testbench, then discusses advantages and disadvantages of using Vivado and Questa Core for verification.

It's always challenging to take over a complex testbench from another engineer who is no longer on the given project. In this presentation, we walk through 5 steps you can take to fully understand a “new to you” UVM testbench.

In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project -- a powerful flow that increases the confidence of D&V teams at sub-system and top-level integration.

Verification IQ, a new web-based virtual platform to overcome the complexity of Coverage analysis and closure; enabling our engineering teams to collaborate in real-time to achieve closure quicker, and accelerate time-to-market.

In this session we review the challenges that AI/ML tech poses for the safety of Autonomous Driving Vehicles, and how to quantitatively measure Diagnostic Coverage of an AI design to get this technology safely into the car's ICs.

This presentation will explain new, enhanced randomization and functional coverage features in UVVM, and how this will help you make better VHDL testbenches.

The DFT team needs a separate VC file for each physical partition to perform the DFT insertion. This presentation demonstrates how the automation from Quest Visualizer is used to create the VC list for all physical partitions.

This presentation demonstrates how the Questa Visualizer Profiler was used to identify areas for improvement within Arm Verification IP components and the reductions to simulation time that were achieved.

In this presentation we talk about the steps taken to do exhaustive, formal-based connectivity checks on a design where the only available information about the signal connections was a Tcl file from a 3rd party tool.

Fermilab introduces its partnership with Siemens to provide full integration with Catapult HLS design and verification flow. They describe projects that have benefitted from hls4ml and outline future directions.

RTL power optimization is key for creating energy-efficient designs that meet power budgets and address potential reliability and thermal issues early. NXP will share their insights on implementing these techniques.

Learn how Samsung extracted from physically aware cycle-by-cycle power analysis to find windows of interest. These windows can be input into a downstream power signoff tool, enabling fast, accurate, and reliable power signoff.

ORNL with the help of the Siemens EDA tools, including Catapult HLS, the neuromorphic accelerator is being adapted from an FPGA prototype to a more capable and lower-power ASIC implementation.

One of the solutions for increasing requirements for shorter time to market, Nokia has explored is raising abstraction level in both RTL design and verification with the help of High-Level Synthesis and Verification tools.

Discover the ease of use and the value-add of the HLS methodology in an automotive context, with the adoption of SystemC for High-Level-Synthesis replacing the traditional RTL design flow.

Through HLS and their innovative modular system, STMicroelectronics continues to lead in the seamless integration of digital intelligence into analog native products, setting new standards for efficiency and market responsiveness.

This session will introduce High-Level Synthesis, a technology that allows a developer to take a C++ function and automatically compile it into an RTL hardware description, suitable to be deployed into an ASIC or FPGA.

Introducing the concept of last shift cycle simulation in ATPG; evaluates the last n shift cycles before capture. This presentation shares the benefits seen in test coverage and pattern count for ATPG in large complex designs.

Introducing Tessent Streaming Scan Network (SSN) and its use cases: optimizes ATPG and diagnosis, reduces scan test data and enables efficient multi-core testing, lowers ATPG test risk and streamlines DFT signal distribution.

To tackle trace/debug challenges, Kalray used Tessent Embedded Analytics Enhanced Trace Encoder IP. Embedded features like branch prediction and jump target cache achieved high compression, optimizing system performance.

Jay Jahangiri, Product Managing Director for Tessent DFT talks about shift-left DFT techniques including RTL complexity analysis, RTL test points analysis and insertion, and RTL flow optimization with quick synthesis.

Explore Tessent Streaming Scan Network (SSN) as it transforms scan data delivery using packetized data, optimizes packet fill rates for efficient testing, and eliminates manual IO balancing.

Lee Harrison reviews the challenges for DFT engineers with today’s complex designs and how EDA technology is advancing to meet those challenges of technology scaling, design complexity and system level integration and monitoring.

The shift to 3D stacked ICs brings testing challenges, especially for die-to-die interconnects. Using Tessent's UDFM, we precisely model defects to optimize ATPG for better test coverage.

Explore Tessent diagnosis with and without layout-aware features, test flows, validation pre-silicon, and outcomes post-silicon. Analyze ATE failure data to improve identifying failure suspects with layout-aware diagnosis.

This presentation compares Test Points vs. OST across three chips, highlighting their impact on test speed, area, and power consumption in automotive applications.

Explore AI design challenges in DFT, highlighting the shift from traditional to future solutions, implementation complexities, test challenges, and how advanced DFT strategies enhance scalability, efficiency, and silicon results.

Interconnect advances drive 2.5D/3D disaggregated products, posing test challenges but enabling test time reduction via concurrency. Learn about Intel's testing strategy and Siemens' SSN for cutting test time and cost.