User2User content library

User2User: Learn how 3DICs enhance system performance and compactness but challenge verification with their complex tech layers. We'll discuss methodologies, standards, and solutions, including Siemens XSI & Calibre 3DSTACK uses.

User2User: Learn how 3DIC verification faces complex challenges. We address these using Siemens XSI and Calibre 3DSTACK, focusing on DRC, LVS, and assembly checks for high-end systems.

User2User: Learn how 3DIC tech enhances compact, high-performance systems but faces verification challenges. We explore solutions and methodologies, including the use of Siemens XSI and Calibre 3DSTACK.

User2User: Learn how Siemens addresses DRC, LVS, & assembly verification using EDA tools like Siemens XSI & Calibre 3DSTACK. We present a workflow for efficient verification across complex layers

User2User: Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

User2User EU: The speaker concludes by highlighting the need for exploration of hardware/software architectures and co-optimization for automotive applications.

User2User EU: This video provides examples of capabilities within EDM tools like automation, configuration, and APIs to integrate with other systems.

User2User EU: EMIB technology and the provided design kits enable connecting multiple chips with different design rules, and the speaker outlines the overall design flow.

User2User EU: This video provides background on IMEC, a research institute based in Belgium focused on semiconductor research and development.

User2User EU: This video provides background on their company, Swiss, which manufactures memory products in Berlin, Germany with complete in-house production capabilities.

Learn how NVIDIA leveraged Solido Additive Learning technology to speedup standard cell library verification with Solido Design Environment while maintaining the same accuracy on verifying a new PDK revision.

Learn how Allegro MicroSystems leveraged AI-powered Solido Design Environment and Analog FastSPICE to accelerate PMIC verification, resulting in an overall 5X reduction in verification time.

Learn how SiTime leverages AFS, Symphony and Solido Design Environment to ensure seamless integration between the analog and digital components and accelerate verification of high precision MEMS based oscillators SoC.

Learn how Microsoft leverages Solido IP Validation to address IP quality issues early in the design process, saving time and money on potential (ECOs), improving overall IP quality in production and integration flows.

Watch this session and learn how to leverage AWS cloud capacity for full cloud migration or peak demand expansion for custom IC verification workloads, and achieve faster time-to-market.

In this presentation we will share results from our customer partnerships on how AI/ML is helping them with particular verification needs. The common thread: ML provides significant value by improving productivity and accuracy.

In this presentation we dive deep into one of the most complex protocols: PCIe IP and the related testbench architecture; and how we adopted Siemens’ PCIe Avery Verification IP in multiple projects.

In this presentation we share how we worked with a customer to migrate from a sophisticated array of home-grown spreadsheets and scripts to process and coverage analysis automation with Questa Verification IQ.

This presentation starts with the introduction of our FPGA-based SoC control system DUT and testbench, then discusses advantages and disadvantages of using Vivado and Questa Core for verification.

It's always challenging to take over a complex testbench from another engineer who is no longer on the given project. In this presentation, we walk through 5 steps you can take to fully understand a “new to you” UVM testbench.

In this session we are presenting a fusion of formal and dynamic verification methods we applied in a mixed signal IC project -- a powerful flow that increases the confidence of D&V teams at sub-system and top-level integration.

Verification IQ, a new web-based virtual platform to overcome the complexity of Coverage analysis and closure; enabling our engineering teams to collaborate in real-time to achieve closure quicker, and accelerate time-to-market.

In this session we review the challenges that AI/ML tech poses for the safety of Autonomous Driving Vehicles, and how to quantitatively measure Diagnostic Coverage of an AI design to get this technology safely into the car's ICs.

This presentation will explain new, enhanced randomization and functional coverage features in UVVM, and how this will help you make better VHDL testbenches.

The DFT team needs a separate VC file for each physical partition to perform the DFT insertion. This presentation demonstrates how the automation from Quest Visualizer is used to create the VC list for all physical partitions.

This presentation demonstrates how the Questa Visualizer Profiler was used to identify areas for improvement within Arm Verification IP components and the reductions to simulation time that were achieved.

In this presentation we talk about the steps taken to do exhaustive, formal-based connectivity checks on a design where the only available information about the signal connections was a Tcl file from a 3rd party tool.

User2User EU: This video highlights the key challenges and learnings around thermal management, SI, Power delivery design and manufacturability for complex space products.

User2User EU: This video discusses the importance of starting DFX early during component creation in PLM rather than later at layout, and getting continual feedback from production to improve over time.

User2User EU: This video provides background on how Phillips has used Xpedition EDM for 15 years with heavy customization and integrations.

User2User EU: This video provides an overview of Sky's products like the Q set-top box, broadband routers, the Entertainment OS, and experimental products like the Live camera.

User2User EU: This video explains how IPC extracted design requirements from their standards to create generic DFM rule sets and profiles in PCBflow.

User2User EU: This video discusses the increasing challenges with DDR5 and LPDDR5 simulations and design compared to previous generations like DDR4, due to faster clock speeds and less timing margin.

User2User EU: This video introduces the topic of power module optimization and explains the motivation behind developing a fully automated optimization process.