1. Home
  2. Events
  3. Tessent at ITC
An evening cityscape of San Diego, Calif.

November 4-7 | San Diego, California

International Test Conference 2024

A design-for-test (DFT) market leader, we're a Diamond Supporter for International Test Conference (ITC) North America. We'll showcase the latest Tessent DFT solutions that help customers address complex system-on-a-chip (SoC) debug, test, yield, safety, security and optimization requirements.

Booth 207

Visit Tessent in booth 207 to learn more about our industry-leading DFT solutions. We deliver innovative solutions that mitigate risks throughout the integrated circuit (IC) lifecycle to make testing smarter and more efficient.

Diamond event

Join us in the Sapphire-CDGH at 10:45 a.m. on Tuesday, Nov. 5, for the Diamond Supporter presentation to hear exciting and exclusive DFT technology news.

Theater presentations

Join Tessent in our theater on the exhibit floor during open exhibitor hours, where customers, partners, and Siemens experts will present on key DFT topics.

Join us

Join us at ITC to hear our customers and subject matter experts talk about the new technologies Tessent is using and what is coming in the near future.

Select...

Sunday, Nov. 3, 2024

8:30 a.m. - noon | Hierarchical and tile-based DFT techniques for AI and large SOC

Lee Harrison, Siemens EDA | Sapphire 411

In this tutorial, we will give an overview of the exciting field of AI and high-performing computing (HPC). It will cover the critical and special characteristics, as well as the architecture of the popular AI chips. We will summarize the features of the AI chips from DFT perspective and introduce the DFT technologies that can help with testing AI chips, and also examine how the shift to 2.5D and 3D, including chipset development, is changing the industry and creating new challenges for the DFT community. Finally, we will present case studies on how DFT is implemented in AI chips. We will also present some of the functional monitoring techniques available today, provide an overall architecture showing how functional monitoring can be implemented and discuss how the data can be used to manage in-life capabilities.

1 p.m. - 4:30 p.m. | Mixed-signal DFT challenges and solutions

Stephen Sunter, Siemens EDA | Sapphire 411

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We review widely used basic DFT techniques; fault simulation; IEEE 1149.1/4/6/7, 1687 and ISO 26262 metrics; built-in self-test (BIST) for analog-to-digital converters (ADC)/digital-to-analog (DAC), phase-locked loop (PLL), serializer/deserializer (SerDes)/ double data rate (DDR); and random analog. We will present essential principles of practical analog BIST and practical DFT techniques, from quicker analog defect simulation to DFT that focuses on simplicity, diagnosis, reuse and automation. We will conclude with a detailed summary of the Analog Defect Coverage and Analog Test Access standards (IEEE P1687.2, P2427), as they approach completion.

Certification: These tutorials qualify for credit towards IEEE Computer Society Test Technology Technical Council (TTTC) certification under the IEEE Computer Society TTTC program.

Setup on-site meeting

Joining us in San Diego for ITC this year? Schedule a chat with one of our on-site experts or drop by our booth. Schedule a meeting, and send your contact information, along with details of when you are free during the show, and we will connect you with one of our on-site experts.

Conference room meeting between three people sitting at a table