November 4-7 | San Diego, California
International Test Conference 2024
A design-for-test (DFT) market leader, we're a Diamond Supporter for International Test Conference (ITC) North America. We'll showcase the latest Tessent DFT solutions that help customers address complex system-on-a-chip (SoC) debug, test, yield, safety, security and optimization requirements.
Booth 207
Visit Tessent in booth 207 to learn more about our industry-leading DFT solutions. We deliver innovative solutions that mitigate risks throughout the integrated circuit (IC) lifecycle to make testing smarter and more efficient.
Diamond event
Join us in the Sapphire-CDGH at 10:45 a.m. on Tuesday, Nov. 5, for the Diamond Supporter presentation to hear exciting and exclusive DFT technology news.
Theater presentations
Join Tessent in our theater on the exhibit floor during open exhibitor hours, where customers, partners, and Siemens experts will present on key DFT topics.
Join us
Join us at ITC to hear our customers and subject matter experts talk about the new technologies Tessent is using and what is coming in the near future.
Sunday, Nov. 3, 2024
8:30 a.m. - noon | Hierarchical and tile-based DFT techniques for AI and large SOC
Lee Harrison, Siemens EDA | Sapphire 411
In this tutorial, we will give an overview of the exciting field of AI and high-performing computing (HPC). It will cover the critical and special characteristics, as well as the architecture of the popular AI chips. We will summarize the features of the AI chips from DFT perspective and introduce the DFT technologies that can help with testing AI chips, and also examine how the shift to 2.5D and 3D, including chipset development, is changing the industry and creating new challenges for the DFT community. Finally, we will present case studies on how DFT is implemented in AI chips. We will also present some of the functional monitoring techniques available today, provide an overall architecture showing how functional monitoring can be implemented and discuss how the data can be used to manage in-life capabilities.
1 p.m. - 4:30 p.m. | Mixed-signal DFT challenges and solutions
Stephen Sunter, Siemens EDA | Sapphire 411
This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We review widely used basic DFT techniques; fault simulation; IEEE 1149.1/4/6/7, 1687 and ISO 26262 metrics; built-in self-test (BIST) for analog-to-digital converters (ADC)/digital-to-analog (DAC), phase-locked loop (PLL), serializer/deserializer (SerDes)/ double data rate (DDR); and random analog. We will present essential principles of practical analog BIST and practical DFT techniques, from quicker analog defect simulation to DFT that focuses on simplicity, diagnosis, reuse and automation. We will conclude with a detailed summary of the Analog Defect Coverage and Analog Test Access standards (IEEE P1687.2, P2427), as they approach completion.
Certification: These tutorials qualify for credit towards IEEE Computer Society Test Technology Technical Council (TTTC) certification under the IEEE Computer Society TTTC program.
Tuesday, Nov. 5, 2024
10:45 a.m. - 11:45 p.m. | Sapphire CDGH
- Ankur Gupta, SVP and GM of Digital Design Creation Platform with Siemens EDA - Gives a Siemens’ transformative technologies review plus an introduction to an important new product that deals with in-system test
- Dan Trock, Principal Engineer, Amazon Web Services, Annapurna Labs - Describes how this new technology is already in silicon at Amazon
- Vishal Agarwal, Sr. Director, H/W Engineering with NVIDIA - Describes how NVIDIA has used Tessent Streaming Scan Network in challenging designs
- Anurag Jindal, Head of DFX group with Ericsson – Presents productivity gains using Tessent products
Check back for more information on theater presentations.
Tuesday, Nov. 5, 2024
4:00 p.m. | From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel
Siemens, Intel | Sapphire KL
4:00 p.m. | Bus-backed Packetized Scan Architecture Trade-offs for Hetrogeneous Multi-Die S0Cs
Siemens, Renesas | Sapphire OP
5:20 p.m. | A Cell-Aware Transistor State Stress Model and its Application for Quality Measurement
Siemens | Sapphire KL
Wednesday, Nov. 6, 2024
10:30 a.m. | Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Siemens | Sapphire OP
10:30 a.m. | High-bandwidth IJTAG over SSN
Siemens, Intel | Aqua Salon AB
11:30 a.m. | Delay Monitoring Under Different PVT Corners for Test and Functional Operation
Siemens, Purdue University | Sapphire OP
2:00 p.m. | Diagnosis of Intermittent Faults and Corresponding Algorithm Development Beyond 5nm Technologies
Siemens, Samsung | Aqua Salon AB
4:30 p.m. | MBIST-Based MRAM Defect Screening for Safety-Critical Applications
Siemens, Karlsruhe Institute of Technology | Aqua Salon AB
5:00 p.m. | Digital Scan and ATPG for Analog Circuits
Siemens | Sapphire KL
Thursday, Nov. 7, 2024
10:30 a.m. | Power-Aware Test Scheduling for Memory BIST
Siemens, Poznan University of Technology | Sapphire OP
11:00 a.m. | Deterministic In-Fleet Scan Test for a Cloud Computing Platform
Siemens, Amazon Web Services, Poznan University of Technology | Sapphire OP
2:30 p.m. | Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
Siemens, TSMC, Racyics | Sapphire KL
Wednesday, Nov. 6, 2024 | 12:00 p.m. - 2 p.m. | Exhibit Hall - Sapphire ABEFIJMN
Enhancing Test Quality for Abutted Designs with Logic BIST
Siemens
Flexible Scan Test Architecture with Scalable Bus in 2.5D-3D Packaging Chips
Siemens, Broadcom
Accelerated 3D IC DFT Development Using Commercial Multi-die Solution
Siemens, Broadcom
Cell-Aware Chain Diagnosis for Backside Power
Siemens
Layout-Aware Chain Diagnosis for Backside Power
Siemens
Driving Deterministic In-System Test Using Advanced Peripheral Bus (APB)
Siemens, ARM
Improved area overhead with advanced memory dump and memory test automation for AI chips
Siemens, Google
Efficient Test Port Access to Address Test Time
Siemens, Intel
Effective Detection of Uncommon Faults by SMarchCHKBvcd algorithm
Siemens
Embedded Trace: A Key Enabler for Silicon Debug and Continuous Monitoring
Siemens
Meet Siemens Experts
Join Tessent experts to hear about our most successful product endeavors. Bring your questions to these first-come, first-served sessions.
8-9am | Aqua 300B
Meet with Jeff Mayer and Lee Harrison to talk about in-field and in-system testing.
8-9am | Aqua 300B
Meet Pete Orlando, Product Manager for Tessent Streaming Scan Network.
Setup on-site meeting
Joining us in San Diego for ITC this year? Schedule a chat with one of our on-site experts or drop by our booth. Schedule a meeting, and send your contact information, along with details of when you are free during the show, and we will connect you with one of our on-site experts.
