October 8-13 | Anaheim, California
International Test Conference 2023
Siemens, a DFT market leader, is proud to be the Diamond Supporter for ITC North America. For 2023, we will be showcasing the latest Tessent DFT solutions that help customers address their debug, test, yield, safety, security & optimization requirements for complex SoCs.
Siemens EDA | Tessent Silicon Lifecycle Solutions
DFT market-leading solutions
Tessent, the industry leader in DFT, delivers innovative solutions that mitigate risks throughout the IC lifecycle & make testing smarter & more efficient. Products include Tessent SSN (Streaming Scan Network) & Tessent Multi-die.
Diamond Supporter presentation
Join us in the Grand Ballroom at ITC at 10.45 am on Tuesday, October 10, for exciting and exclusive DFT technology news. More details provided below.
Theater presentations live in booth #205
Join Tessent in our theater on the exhibit floor during open exhibitor hours, where customers, partners, and Siemens experts will present on key DFT topics.
Siemens EDA hosts ITC Diamond Event
This year’s Diamond Event features Darshan Kobla, Senior Director with Microsoft. Darshan’s presentation Smart DFT for Complex Semiconductor Design will describe DFT challenges with modern silicon designs. He will cover plug-and-play DFT architectures and solutions that enable extremely fast development and device bring-up. Darshan leads test strategy for all product segments at Microsoft.
Tessent design for test at ITC
DON'T MISS THE SPECIAL SIEMENS DIAMOND EVENT
Tuesday, October 10 at 10:45 am following the plenary session, in the Disney Grand Ballroom Center. Darshan Kobla, Senior Director at Microsoft, will describe some of the challenges with the modern silicon designs in his presentation titled Smart DFT for Complex Semiconductor Designs.
Be sure to attend our Diamond Supporter presentations for some exclusive news and announcements including:
- Shift Left product announcement
Nilanjan Mukherjee, Senior Director of Engineering for Tessent, Siemens - Smart DFT for Complex Semiconductor Design
Darshan Kobla, Senior Director with Microsoft - How to engineer a smarter future faster
Ankur Gupta, VP/GM of Silicon Lifecycle Solutions, Siemens
LIVE TESSENT THEATER PRESENTATIONS
Open daily to all attendees during exhibit hours.
Join Tessent in booth #205, where customers, partners and Siemens will present live on our latest DFT solutions and key DFT topics, including:
- Tessent Streaming Scan Network (SSN) - a once in a decade technology
- SSN for In-system test
- SSN on-the-fly optimization
- Diagnosis with SSN
- 3D IC solution - Tessent Multi-die
- Tile-based design automation
- ATPG Boost
- Yield learning to boost manufacturing yields
- Measuring analog test coverage
Setup on-site meeting
Joining us in Anaheim for ITC this year? Schedule a chat with one of our on-site experts or drop by our booth. Click the link below and send your contact information along with details of when you are free during the show and we will get you connected with one of our on-site experts.
Tessent Technical Tutorials
1:00 - 4:30pm | MIXED-SIGNAL DFT CHALLENGES AND SOLUTIONS
Stephen Sunter, Siemens EDA
This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that focuses on simplicity, diagnosis, reuse, and automation. We conclude with a detailed summary of the Analog Defect Coverage and Analog Test Access standards (IEEE P1687.2, P2427), as they approach completion thanks to the effort of dozens of people over many years.
1:00 - 4:30pm | HIERARCHICAL AND TILE BASED DFT TECHNIQUES FOR AI AND LARGE SOC
Lee Harrison, Pete Orlando, Siemens EDA
In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.
Certification: These tutorials qualify for credit towards IEEE TTTC certification under the TTEP program.
Tessent technical presentations | Schedule
Tuesday, October 10
1:30 pm | A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy
Oussama Laouamri, Siemens | Magic Kingdom Ballroom 1
4:40 pm | Global control signal defect diagnosis in volume production environment
Piotr Zimnowlodzki, Siemens | Magic Kingdom Ballroom 1
Wednesday, October 11
POSTERS | 12:00 - 2:00pm | Expo Floor
Thursday, October 12
11:00 am | Predicting the resolution of scan diagnosis
Jakub Janicki, Siemens EDA | Magic Kingdom Ballroom 2
1.30 pm | Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Saidapet Ramesh, NXP with Siemens EDA | Magic Kingdom Ballroom 1
1.30 pm | Will Silent Data Errors give a new lease on life to Semiconductor Test?
PANEL SESSION | Moderator: Anne Meixner, Semiconductor Engineering | Magic Kingdom Ballroom 3
Silent Data Corruption panel
Join us in the Magic Kingdom Ballroom 3 where Anne Meixner with Semiconductor Engineering monitors a discussion among a diverse panel of industry experts that include:
- Sandeep Bhatia (Google)
- Sankar Gurumurthy (AMD)
- David P. Lerner (Intel)
- Jennifer Dworak (SMU)
- Janusz Rajski (Siemens DISW)
- Noam Brousard (proteanTecs)
This illustrious group will discuss the primary contributors of SDE, how test quality in this area can be improved and how to deal with the ever-increasing number of test patterns without affect test cost.
Workshops
Details coming soon