International Test Conference 2023

1:00 - 4:30pm | MIXED-SIGNAL DFT CHALLENGES AND SOLUTIONS

Stephen Sunter, Siemens EDA

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that focuses on simplicity, diagnosis, reuse, and automation. We conclude with a detailed summary of the Analog Defect Coverage and Analog Test Access standards (IEEE P1687.2, P2427), as they approach completion thanks to the effort of dozens of people over many years.

1:00 - 4:30pm | HIERARCHICAL AND TILE BASED DFT TECHNIQUES FOR AI AND LARGE SOC

Lee Harrison, Pete Orlando, Siemens EDA

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

Certification: These tutorials qualify for credit towards IEEE TTTC certification under the TTEP program.

Join us in the Magic Kingdom Ballroom 3 where Anne Meixner with Semiconductor Engineering monitors a discussion among a diverse panel of industry experts that include:

• Sandeep Bhatia (Google)
• Sankar Gurumurthy (AMD)
• David P. Lerner (Intel)
• Jennifer Dworak (SMU)
• Janusz Rajski (Siemens DISW)
• Noam Brousard (proteanTecs)

This illustrious group will discuss the primary contributors of SDE, how test quality in this area can be improved and how to deal with the ever-increasing number of test patterns without affect test cost.