September 27-29 | Anaheim, California
Join Tessent at the International Test Conference 2022
ITC is the world's premier conference dedicated to electronics test. This year's ITC continues its mission to play a unique role as an information-sharing forum, where the wide range of its offerings allows ITC delegates to learn, network and conduct business.
Siemens EDA | Tessent Lifecycle Solutions
Adaptive Intelligence Solutions
Tessent will showcase a new category of continuously learning applications that makes testing smarter and more efficient.
Diamond Supporter presentation
Join us in the Grand Ballroom at ITC at 11 am on Tuesday, September 27, for some special and exclusive technology news. More details below.
Theater presentations live in booth #115
Join Tessent in our theater on the exhibit floor during open exhibitor hours, where customers, partners, and Siemens experts will present on key DFT topics.
Tessent design for test at ITC
DIAMOND SUPPORTER PRESENTATION
Tuesday, September 27 at 11:00 am following the plenary session at the Grand Ballroom
Be sure to attend our Diamond Supporter presentation for some exclusive news and announcements.
- DFT to In-Life monitoring for dependable electronic systems
Ankur Gupta, VP/GM of Tessent products, Siemens, Introduction - Reducing Design Effort, Test Time and Power with SSN in AWS Custom Silicon
Dan Trock, Amazon - Advancements in DFT automation for 2.5D / 3D IC era
Vidya Neerkundar, Siemens - Structural Deterministic Test in Silicon Lifeycle
Janusz Rajski, Siemens
LIVE TESSENT THEATER PRESENTATIONS
Open daily to all attendees during exhibit hours.
Join Tessent in booth #115, where customers, partners and Siemens will present live on key DFT topics, including:
- Tile-based design automation
- Streaming Scan Network on-the-fly optimization
- Streaming Scan Network for In-system test
- ATPG Boost
- Diagnosis with Tessent SSN
- 3D IC
- Yield learning to boost manufacturing yields
- Measuring analog test coverage
Technical presentations
POSTERS | 12:30 - 2:30 pm | Expo Floor
2:30 - 4:00 pm | SESSION PO
- PO.18 IR-Drop Improvement with Packet-Based Scan
J. Reynick, Siemens EDA
S. Alampally, Broadcom - PO.35 Design for test (DFT) Considerations when Designing Tile-based/abutted Physical Blocks
V. Neerkundar, Siemens
2:30 - 4:00 pm | SESSION A4 | HW SECURITY II
- A4.4 Hardware Root of Trust for SSN-based DFT Ecosystems
J. Tyszer, B. Wlodarczak, Poznan University of Technology
J. Rajski, M. Trawka, Siemens Digital Industries Software
2:30 - 4:00 pm | SESSION C4 | MEMORY TEST/REPAIR
- C4.1 Configurable BISR Chain For Fast Repair Data Loading
W. Zou, B. Nadeau-Dostie, Siemens EDA
4:30 - 6:00 pm | SESSION B5 | ANALOG TESTING
- B5.3 IEEE P1687.1: Extending the Network Boundaries for Test
M. Laisne, H. von Staudt, Dialog Semiconductor - a Renesas Company
A. Crouch, Amida Technology Solutions, Inc.
M. Portolan, Univ Grenoble Alpes, CNRS
M. Keim, Siemens Digital Industries Software
B. Van Treuren, VT Enterprises Consulting Services
J. Rearick, Advanced Micro Devices
S. Zuo, Tailored Management
Technical presentations
10:30 - 12:00 pm | Session B6 | Scan-Based Learning and Diagnosis
- B6.2 Industry Evaluation of Reversible Scan Chain Diagnosis
S. Urban, J. Janicki, M. Sharma, W-T. Cheng, Siemens EDA
M. Parley, K. Chung, S. Nicholson, S. Mittal, Qualcomm
1:30 - 3:00 pm | Session A7 | Test Generation
- A7.2 DIST: Deterministic In-System Test with X-masking
J. Tyszer, B. Wlodarczak, Poznan University of Technology
G. Mrugalski, J. Rajski, Siemens Digital Industries Software - A7.3 Test Generation for an Iterative Design Flow with RTL Changes
J. Joe, I. Pomeranz, Purdue University
N. Mukherjee, J. Rajski, Siemens Digital Industries Software
1:30 - 3:00 pm | Session C7 | Special Session
- Design-for-Verification (DfV): A New Direction in Design Qualification
A. Majumdar (Moderator) Presenters: D. Akselrod, A. Banover, P. Yousefpour, AMD