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An overhead view of a ship, split down the middle. The left half shows a neon blue digital twin against a dark background, while the right half shows the ship in realistic detail on a blue ocean.

Siemens EDA at GOMACTech

March 9-12, 2026 | New Orleans, LA

Gold Sponsor

Join Siemens EDA at GOMACTech 2026

Siemens empowers defense innovation through advanced digitalization. Join our experts to discover solutions that accelerate your mission, from AI-powered design to comprehensive digital twins.

Two computer processors are shown against a dark blue background. The left is a physical component with gold pins visible on its underside. The processor on the right is a digital twin, showing its internal circuitry.

Engineer a smarter future, faster - booth #120

Siemens software allows you to develop more cost-effective electronic systems, components, and products.

Software defined

Hardware abstraction is now essential - explore and validate software before expensive silicon commits in an era where design mistakes cost millions.

AI powered

Close the widening productivity gap as AI-chip complexity explodes - human designers need AI augmentation to keep pace with exponential design challenges.

Silicon enabled

Next-generation applications demand flawless execution - nanometer-level precision engineering is no longer optional but critical for competitive survival.

Expert sessions

Presentations you won't want to miss! Stop by meeting room 272 to hear insights from industry experts.

Select...
  • 12:30pm - 12:50pm - Systemic PDN Analysis for Advanced Packaging Architectures
    John Caka | SI / PI Applications Engineer | Siemens EDA

    Traditional package and PCB analysis tools face significant limitations when applied to advanced 2.5D/3D packaging, including inadequate modeling of fine-pitch interconnects and inability to capture electromagnetic coupling in dense chiplet configurations. The unique challenges of analyzing silicon versus organic architectures—stemming from vastly different material properties, thermal characteristics, and electrical behaviors—require enhanced simulation capabilities beyond conventional methodologies. Additionally, the industry faces significant workflow challenges due to the mixing of silicon-based design and analysis tools with package and system-level tools, creating data translation bottlenecks, model inconsistencies, and design iteration delays that impede efficient PDN analysis and optimization across the complete chiplet-system hierarchy.

    This paper presents a comprehensive PDN analysis methodology specifically tailored for advanced packaging technologies: (1) DC analysis for voltage regulation and current distribution optimization with advanced meshing for fine-pitch structures, (2) AC decoupling analysis utilizing 2.5D and 3D electromagnetic solvers for multi-die coupling effects, and (3) transient droop analysis employing time-domain methods optimized for chiplet power delivery scenarios. We demonstrate how traditional Package and PCB analysis tools can be extended for advanced packaging requirements, including specialized modeling for silicon-based architectures and enhanced material property handling for heterogeneous substrates. The approach addresses tool integration challenges by establishing seamless data flow between silicon EDA environments and package-level analysis platforms using Siemens EDA analysis software enabling unified PDN verification across multiple design domains. The methodology's effectiveness is validated through analysis of representative Intel 3DIC designs: a baseline 2.5D design, and a 2.5D design with Embedded Multi-die Interconnect Bridge (EMIB) technology. This work provides a systematic framework for robust PDN design in next-generation advanced packaging solutions while bridging the gap between silicon and package design tools.


  • 1:00pm - 1:20pm - System Verifier framework overview
    Ahmed Hamaza | Solution Architect | Siemens EDA

    Explosive software growth in software-defined and AI-driven electronic systems amplifies non-deterministic failures and late-stage "integration hell." Traditional verification—built for deterministic hardware—falls short in providing timely, objective correctness evidence for adaptive architectures. This presentation introduces a purpose-built verification framework offering continuous coverage from high-level requirements to low-level implementation. It employs a minimalist, repeatable pattern: natural-language requirements become parameterized constraints, hierarchically allocated across black-box, gray-box, and white-box views.

    Verification Capture Points (VCPs)—structured artifacts tracking methods, execution history (with failures), evidence, and status—ensure transparent, auditable progress. Interoperable with SysML v2, it uses the standardized model repository as a collaborative "GitHub for systems models," sidestepping MBSE technical debt. Tool-agnostic and federated via open standards, it integrates best-in-class or legacy tools without lock-in, duplication, or migration—enabling early issue detection and reduced integration risk in complex cybertronic systems.


  • 1:30pm - 1:50pm - Moving beyond generic PCB solutions to A&D relevant System Design
    Ken Biermann | Member of Technical Staff | Siemens EDA

    The Siemens Systems software portfolio covers PCB ideation, creation, simulation, analysis, and integration throughout the PCB ecosystem. This session provides an overview of topics which are highly relevant to the A&D industry:

    • AMS simulation topics including rad hard AMS simulation
    • Worst-case and component stress analyses
    • Requirements systems for traceability/provability
    • Supply Chain connectivity and early visibility for Engineering



  • 2:00pm - 2:20pm - Questa One + Agentic AI: Transforming Verification Through Unification and Intelligence
    Moses Satyasekaran | Questa Product Line Director | Siemens EDA

    Questa One delivers a unified verification platform that eliminates tool fragmentation and accelerates your workflows. Agentic AI amplifies this with AI-powered assistance generating verification plans from specs, automating lint and property creation, debugging failures, closing coverage gaps, and many more intelligent capabilities. Experience demos of both the platform and AI capabilities that are transforming how teams achieve verification closure.


  • 2:30pm - 2:50pm - System of Systems Verification and Validation with Hardware Assisted Verification
    Andy Meier | Director, Product Management Hardware Assisted Verification | Siemens EDA

    In the Government and Aerospace market, the complexity of System-on-Chip (SoC) designs necessitates robust and efficient verification methodologies. This presentation will explore the significant value of Hardware-Assisted Verification (HAV) in accelerating the verification and validation of these intricate 'Systems of Systems.' We will delve into how Siemens EDA's Veloce Emulation and Veloce proFPGA CS, along with their rich ecosystems, provide unparalleled capabilities for achieving comprehensive design validation. A key focus will be on demonstrating how a connected verification path between simulation and emulation dramatically improves 'time to emulation,' enabling faster turnaround times for critical projects. Furthermore, we will discuss practical methodologies employed by leading customers and illustrate how HAV is instrumental in achieving thorough validation of your digital twin, ensuring mission-critical reliability and performance.


  • 3:00pm - 3:20pm - Redesigning Chip Design with Generative and Agentic AI using Fuse EDA AI System
    David Abercrombie | Sr. Director, Calibre Product Management | Siemens EDA

    The semiconductor industry is shifting from hardware-defined to software-defined models, increasing demands for chip designers and on the productivity of EDA tools. To address this, Siemens created the Fuse EDA AI System.

    Fuse is a secure, purpose-built generative and agentic AI system for semiconductor and PCB design. Centered on openness, it allows customers to integrate proprietary data into custom workflows with flexible on-premises or cloud deployment options. A centralized multimodal data lake drives productivity by leveraging advanced LLMs, RAG, and agentic methodologies, while support for NVIDIA, including NIM and a Nemotron model, further accelerates inference and high-context reasoning.

    These powerful AI capabilities are integrated across the entire Siemens EDA portfolio, increasing productivity across the EDA workflow: from HLS to digital verification, to physical verification, and board design. Fuse also accelerates verification and design flows within complex 3D IC environments, significantly boosting user productivity. By embedding intelligent automation throughout the design flow, Siemens is ushering in the next era of EDA.


  • 3:30pm - 3:50pm - Tessent throughout the silicon lifecycle
    Fady Abushahla | Account Technology Manager, IP & Consulting | Siemens EDA

    Siemens Tessent tools are a comprehensive EDA software suite for integrated circuit (IC) design-for-test (DFT), debugging, and yield enhancement. They automate test pattern generation, increase silicon quality, and reduce test time across the entire chip lifecycle, from RTL design to post-silicon manufacturing and in-system monitoring.

Siemens EDA papers and presentations

Select...
  • 1:30pm - 3:10pm | Room 293
    Systematic PDN analysis for Advanced Packaging Architectures
    Contributors: Siemens - John Caka, Muhammed Hassan, Sudarshan Deo | Intel -Satish Surana, Sadha Parasuraman


  • 1:30pm - 3:10pm | Room 295
    Verification Coverage Traceability for System to Silicon via Verification Capture Points (VCPs)
    Contributors: Siemens - Mike Andrews, Ahmed Hamza

    Executable Digital Twin of a Tera-Op Signal Chain
    Contributors: Siemens - Nilay Mitash, Jeff Laster | Raytheon Technologies - PC Chien, Muru Ramaswami, Davin Swanson, Sean Lee, Kayla May, Jackson Chia, Ken Johnson

    Emulation Isn’t Just for ASICs
    Contributors: Siemens - Mark Baker | Collins Aerospace - Gregory Allen