DVCon USA
March 4 – 7, 2024
DoubleTree by Hilton Hotel
San Jose, CA
Attend our informative tutorial, luncheon, paper, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.
Siemens EDA activities
Accellera: Portable Stimulus Standard
Monday, March 4, 9 a.m. — 12:30 p.m. | Donner
Accellera: Hierarchical CDC and RDC closure with standard abstract models
Monday, March 4, 11 a.m. — 12:30 p.m. | Fir
Data-Driven Design, Verification, Validation, and Signoff Case Studies of RISC-V SoCs
Thursday, March 7, 9 a.m. — 12:30 p.m. | Cascade
When will we be able to say, "EDA-GPT, verify my ASIC"?
Wednesday, March 6, 8 a.m. – 9 a.m. (Oak - Fir)
Goldman Sachs estimates that up to 25% of jobs in the US and a staggering 300 million jobs globally will be affected by generative AI. As contributors to the semiconductor industry, we find ourselves accelerating and impacted by this transformative trend.
While AI and machine learning have already made strides in verification, the advent of Generative AI, particularly Large Language Models (LLMs), introduces fresh possibilities for enhancing verification productivity through acceleration, automation, and heightened accuracy. However, the critical question remains – can these promises materialize?
Many verification teams have either integrated LLMs into their daily workflows or plan to do so. Simultaneously, concerns linger around data privacy, potential job displacement, and role changes.
This panel invites participants to share and discuss their perspectives, experiences, insights, and apprehensions regarding the role of generative AI in verification. By doing so, the panel aims to offer the audience a glimpse into the future of verification, driven by LLMs, which is rapidly approaching.
Panel Participants:
- Moderator:
- Harry Foster, Chief Scientist Verification, Siemens EDA
- Panelists:
- Erik Berg, Principal SoC Verification Engineer, Microsoft
- Daniel Schostak, Verification Architect & Fellow, ARM
- Mark Ren, Director of Design and Automation Research, NVIDIA
- Dan Yu, AI/ML Solutions Manager, Siemens EDA
Large Language Model (LLM) for Verification: A Review and Its Application in Data Augmentation [1135]
Tuesday, 9:00 am - 11:00 am – Oak – Session 2, AI&ML in Verification
New, Innovative Way to Verify Packaging Connectivity [1138]
Tuesday, 9:00 am - 11:00 am – Fir – Session 3, Formal Verification Use Cases
On Analysis of RDC issues for identifying Reset tree design bugs and further strategies for Noise Reduction [1088]
Tuesday, 11:00am - 12:30pm, Poster Session
Without Objection - Touring the uvm_objection implementation - uses and improvements [1116]
Tuesday, 3:00 pm - 5:00 pm – Monterey-Carmel – Session 4, UVM Testbenches
Are My Fault Campaigns Providing Accurate Results for ISO26262 Certification? [1068]
Tuesday, 3:00 pm - 5:00 pm – Oak – Session 5, Functional Safety Verification
Functional Verification from Chaos to Order: Using Continuous Integration in Hardware Functional Verification [1095]
Wednesday, 9:30am - 11:00 am – Monterey-Carmel – Session 7, Regression Management Techniques
Functional Verification of Analog Devices modeled using SV-RNM [1049]
Wednesday, 3:00 pm - 4:30 pm – Fir – Session 12, Analog Modeling in SystemVerilog
How your D-V challenges drive our innovation
The latest trends — the move from monolithic SoCs to chiplets, AI/ML and specialized accelerators, and more — are starting to break current flows, demanding new innovations.
In this fireside chat, EDA veteran Ron Wilson will challenge the panelists to give concrete answers on where performance optimizations are paired with thoughtful solutions to tackle complex, scalable design and verification challenges.
Thursday morning tutorial
Data-driven design, verification, validation, and signoff case studies of RISC-V SoCs
Efficiently delivering a first-time right RISC-V-based SoC requires a flow that supports every phase of the development process, from rigorously validating the RTL with simulation and formal methods, to full SoC testing with real world workloads, to specialized C++ or SystemC HL verification of specialized accelerator IP blocks.
