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DVCON USA background.Design and Verification Conference and Exhibition (DVCON 2024) - United States.


March 4 7, 2024
DoubleTree by Hilton Hotel
San Jose, CA

Attend our informative tutorial, luncheon, paper, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.

Siemens EDA activities

Accellera: Portable Stimulus Standard

Monday, March 4, 9 a.m. — 12:30 p.m. | Donner

Accellera: Hierarchical CDC and RDC closure with standard abstract models

Monday, March 4, 11 a.m. — 12:30 p.m. | Fir

Data-Driven Design, Verification, Validation, and Signoff Case Studies of RISC-V SoCs

Thursday, March 7, 9 a.m. — 12:30 p.m. | Cascade

WEDNESDAY, Noon-1:30 p.m. — PINE

How your D-V challenges drive our innovation

The latest trends — the move from monolithic SoCs to chiplets, AI/ML and specialized accelerators, and more — are starting to break current flows, demanding new innovations.

In this fireside chat, EDA veteran Ron Wilson will challenge the panelists to give concrete answers on where performance optimizations are paired with thoughtful solutions to tackle complex, scalable design and verification challenges.

Design and Verification Conference (DVCON 2024) speakers.
9 a.m. – 12:30 p.m. — Cascade

Thursday morning tutorial

Data-driven design, verification, validation, and signoff case studies of RISC-V SoCs

Efficiently delivering a first-time right RISC-V-based SoC requires a flow that supports every phase of the development process, from rigorously validating the RTL with simulation and formal methods, to full SoC testing with real world workloads, to specialized C++ or SystemC HL verification of specialized accelerator IP blocks.

Design and Verification Conference (DVCON) participants in a session.