DVCon USA
February 24 – 27, 2025
DoubleTree by Hilton Hotel
San Jose, CA
Attend our informative tutorial, luncheon, paper, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.
Siemens EDA Activities
Accellera: Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent
Monday February 24, 9:00am - 10:30am | Fir
Step Function Leaps in RTL Functional Verification Powered by AI/ML Innovations
Monday February 24, 1:30pm - 3:00pm | Monterey Carmel
Power Dynamics: Shaping the Future of the Data Center Era
Monday February 24, 3:30pm - 5:00pm | Fir
Beyond Integers and Floating Point – Designing and Verifying with Alternate Number Representations
Thursday February 27, 9:00am - 10:30am | Donner
CDC/RDC Interchange Format Standard
Thursday February 27, 11:00am – 12:30pm | Siskiyou
Future Proofing Power Intent Specification through Unified Power Format 4.0 for Evolving Advanced State Retention Strategies
Day 1, Session 1: Low Power UPF, [1136]
Static Structural Analysis and Formal Verification of SoC with Software Safety Mechanisms for Functional Safety
Day 1, Poster Session, [1046]
PSS and Protocol VIP: Like a Hand in a Glove
Day 1, Session 4: Portable Stimulus, [1123]
What Just Happened? Behavioral Coverage Tracking in PSS
Day 1, Session 4: Portable Stimulus, [1040]
Design scheme for Emulator-friendly Memory Verification IP to Accelerate Simulation Performance
Day 2, Session 10: Verification IP, [1015]