DVCon USA 2023
February 27 – March 2, 2023
DoubleTree by Hilton Hotel
San Jose, CA
Attend our informative technical keynote, paper, and poster sessions and visit our exhibit booth to learn how Siemens can help you engineer a smarter future faster.
Siemens EDA DVCon US activities
Accellera: Applications for the UVM-AMS Standard
Monday, February 27, 11:00 am – 12:30 pm
Power and Energy Efficient System Design using PowerPro
Monday, February 27, 1:30 pm – 5:00 pm (T4.2)
Mahmud Ullah, Application Engineer
In this workshop, we will be demonstrating why early RTL power and energy estimations are key metrics and how the two metrics have taken a center stage lately in performance-sensitive system design considerations. we will be talking about the RTL Power Analysis as a solution and the challenges associated with it. Also, proposing a regression-ready, error-correcting and fully seamless methodology for an early Power closure at RTL level. We will discuss the key aspects of this methodology like vectorless power linting, Power Analysis, Energy Calculations and the Inputs Qualification for a more reliable power and energy reporting.
Democratizing digital-centric mixed-signal verification methodologies
Monday, February 27, 3:30 pm – 5:00 pm
Verification of inferencing algorithm accelerators
Thursday, March 2, 1:30 pm – 5:00 pm (T2.3)
Russel Klein, Program Director
This workshop will show how to go from Python code in a machine learning framework, like TensorFlow or Caffe, to RTL. As the algorithm is successively refined, at each stage it is necessary to show that both the refinement goals have been achieved and that the implementation has not deviated from the prior design stage. The algorithm will be migrated from Python, to C++, and finally to RTL using High-Level Synthesis (HLS).
Accellera: User Experiences with the Portable Stimulus Standard
Monday, February 27, 9:00 am – 12:30 PM
Jonathan Edwards, Intel, and Prabhat Gupta, AMD
The Accellera Portable Stimulus Standard is moving beyond the “bleeding edge.” As the Portable Stimulus Working Group continues to develop additional features of the language, many companies are adopting the standard in their verification flows. This technical tutorial will begin with an overview of the new features to be included in the coming update to the standard and will feature users from AMD and Intel who will share their experiences using this exciting new technology.
Evolutionary and Revolutionary Innovation for Effective Verification Management & Closure
Thursday, March 2, 9:00 am - 12:30 pm
Joe Hupcey, Darron May, Mark Carey from Siemens EDA
This tutorial will cover the evolution of features and tools to provide efficiency and acceleration to the verification process as well as the revolution required to take full advantage of collaboration, traceability, and emerging technologies provided by machine learning (ML) and virtually unlimited cloud computing resources.
What you will learn:
- How to enhance your current D&V workflow with proven collaboration, requirements traceability, coverage tracking, regression management, and more as inspired by proven technologies from the software world
- How verification planning tools can be integrated with lifecycle management flows by taking advantage of the Open Services for Lifecycle Collaboration standard.
- How ML can be applied to the analysis of the coverage model using analytical navigation to speed understanding and accelerate closure, how ML can complement rules-based systems to improve regression efficiency and debug turn-around times, and how this enables a shift from descriptive to prescriptive analytics with full visibility of the status of projects
- What is required to take full advantage of this kind of massive compute resource scalability with respect to both dynamic reaction and streaming data.
Identifying unique power scenarios with advanced data mining techniques as full SoC (System On Chip) level with real workloads
Tuesday, February 28, 9:00 am - 11:00 am - Monterey Carmel Room
Amir Attarha, Siemens EDA
Pankaj Chauhan, Siemens EDA
Satish-Kumar Agrawal, Siemens EDA
Gaurav Saharawat, Siemens EDA
Diwakar Agrawal, Siemens EDA
Avoiding Configuration Madness The Easy Way
Tuesday, February 28, 9:00 am - 11:00 am - Oak Room
Rich Edelman, Siemens EDA
A survey of Machine Learning Applications in Functional Verification
Tuesday, February 28, 9:00 am - 11:00 am - Monterey Carmel Room
Dan Yu, Siemens EDA
Harry Foster, Siemens EDA
Tom Fitzpatrick, Siemens EDA
What’s Next for SystemVerilog in the Upcoming IEEE 1800 standard
Tuesday, February 28, 3:00 pm - 5:00 pm - Fir Room
Dave Rich, Siemens EDA
Demystifying Formal Testbenches: Tips, Tricks, and Recommendations
Wednesday, March 1, 9:30 am - 11:00 am - Monterey Carmel Room
Shahid Ikram, Marvell
Mark Eslinger, Siemens EDA
Complex Safety Mechanisms Need Interoperability for Validation and Close Loop for Final Metrics
Wednesday, March 1, 3:00 pm - 4:30 pm - Oak Room
Vedant Garg, Siemens EDA
Ann Keffer, Siemens EDA
Samsung co-authors
Tuesday, February 28, 9:00 am - 11:00 am
Do not forget to get your SystemC code covered with UVMC
Vishal Baskar, Siemens EDA
AL-ML Algorithms are Transforming Verification: Separating Hype from Reality
Wednesday, March 1, 1:30 pm – 2:30 pm
Moderator
Shankar Hemmady, Director, Intel
Panelists
Jean-Marie Brunet, VP & GM of Hardware Assistance Verification, Siemens
Lunch & Keynote
Data-Driven Escape from the Verification Pit of Despair
Sponsored Lunch 12:30–13:30 - Pine Cedar
Harry will present the state of verification today based on the findings from the 2022 Wilson Research Group study and then proposes a novel solution to today’s verification crisis.
What Do Farming, Steel, and Space Have in Common?
Keynote 13:30–14:30 - Oak/Fir
With examples from Space Perspective, 80 Acres Farms, and others, we will show you how the new wave of digitalization is driving huge transformations and inspiration for every industry.
It’s about connecting the real and the digital worlds to help everyone innovate faster and adapt to the world better than ever by turning complexity into competitive advantage.
