DVCon Europe 2022

Siemens EDA DVCon Europe activities

Tutorials – Tuesday, December 6

11:45am–1:15pm (T4.2)

A shift-left methodology for early power closure using PowerPro

Mohammed Fahad, Principal Application Engineer

In this session we will present a recommended use model in that power is addressed early. With the available provisions in the tool like early power checking using EDCs and vectorless power clean-up, one must start addressing the power early during the design phase to achieve significant impact. With each revision of the RTL, as we move on during the development phase, the tool should help incrementally reduce the power eventually providing the most power-savvy design. This approach yields better results in terms of power saving impact and time-to-power.

2:15pm–3:45pm (T2.3)

Verification of inferencing algorithm accelerators

Russel Klein, Program Director
Petri Solanti, Application Engineer

This tutorial will show how to verify a machine learning algorithm from Python code in a machine learning framework, like TensorFlow or Caffe, to RTL. As the algorithm is successively refined, at each stage it is necessary to show that both the refinement goals have been achieved, and that the implementation has not deviated from the prior design stage. The algorithm will be migrated from Python, to C++, and finally to RTL using High-Level Synthesis (HLS).

Panel - Wednesday, December 7

9:15am – 10:30am

5G chip design challenges and their impact on verification

Moderator

Gabriele Pulini, Product Marketing and Market Development, Siemens EDA

Panelists

Ashish Darbari, founder and CEO, Axiomise
Oren Katzir, vice president of applications engineering, Real Intent
Herbert Taucher, head of research group, Siemens AG
Anil Deshpande, associate director, Samsung Semiconductor India 
Axel Jahnke, SoC R&D manager, Nokia

Papers - Wednesday, December 7

10:45am – 12:15pm

Register testing – exploring tests, register model libraries, sequences and backdoor access

Rich Edelman, Siemens

3:15pm – 4:45pm

How the right mindset increases quality in RISC-V verification

Philippe Luc, Codasip
Salahhedin Hetalani, Siemens
Nicolae Tusinschi, Siemens

Posters - Wednesday, December 7

12:15pm-12:45pm

Reset your reset domain crossing (RDC) verification with machine learning

Mark Handover, Siemens
Mohamed Badawy, Siemens

Click here to access to the entire DVCon Europe 2022 program grid.