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DAC 2024

Siemens EDA: engineer a smarter future faster

June 23-27 2024 | San Francisco, CA

Design Automation Conference (DAC)
Siemens Booth #2521, Level 2
Moscone West Convention Center

DAC 2024 highlights

Siemens EDA DAC activities

The pace of innovation in electronics is constantly accelerating. To enable customers to deliver life-changing innovations faster and become market leaders, Siemens EDA is committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services.

DAC Pavilion panel

Monday, June 24
11:15 a.m. - noon PDT
DAC Pavilion, Level 2 Exhibit Hall

Bridging the Gaps in Engineering Software for Semiconductors and Systems
Siemens DISW will join Jay Vleeschhouwer, Research Analyst of Griffin Securities, will discuss trends in EDA with other senior executives from leading industrial software companies.

Panelist Speaker: Tony Hemmelgarn, CEO, Siemens Digital Industries Software

Engineering Track

A New Frontier for Floorplanning with AI

A Novel methodology for re-simulation of block vectors helping validate Power Optimization QoR 20x faster

Accelerating IO Liberty Generation through ML based Solution

AI-Assisted Design Optimization for Extensive Design Spaces: Handling 260,000+ Combinations

AI-based High Sigma Verification Methodology for Multiple PVT Corners

AI-Powered High-Sigma Automated Full Library Verification Methodology for Standard Cells

An Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging Technologies

An efficient QA methodology for SRAM libraries

Autonomous Power Sequence validation solution for I/O using Solido Design Environment

Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems

Bus Delay Skew Minimization for High Bandwidth Memory Designs

Critical corners selection for standard cells LVF characterization using AI

Design Automation Advancement in the Analog Domain

Empowering CDC analysis methodology with root cause analysis

Evaluating power, performance, and area for standard cell libraries from different IP providers

High Coverage QA for Process Variability Compensation in LVS Rule Deck

Implementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT Connectivity

Interfacing High-Voltages Directly to Low Power CMOS Process Die for RF, MEMs and Analog Applications

Overcoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip Finishing

Parasitic Leakage Detection in Layout Design

Peak Power Optimization using Active Datapath Operator Profiling

Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization

Resolving the seed promotion due to device layers derivation

Samsung's IP QA methodology using Solido Crosscheck

Shift-left methodology to identify invalid voltage level shifts & validate signal pins' P/G association in IPs/Block's UPF & .LIB views using PERC's static-voltage tracing mechanism

Solving the antenna debug challenge in physical design verification

The Designer's Superpower! Early Circuit Verification with Calibre nmLVS Recon

What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond

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