Siemens EDA: engineer a smarter future faster

High-Level Synthesis Verification Technologies and Techniques

(16 mins, 49 secs)

ST Micro: Using Calibre Design Enhancer Via to Improve Design Quality and Reduce Support Cost

(11 mins, 2 secs)

Microsoft: Focus On IP QA with Solido IP Validation Suite

(7 mins, 57 secs)

Silicon Solutions: PLL Design and Simulation Using Solido SPICE

(26 mins, 34 secs)

Hardware Accelerators – Power and Performance

(16 mins, 46 secs)

Rambus: Challenges of Developing IPs for AI Chips

(12 mins, 58 secs)

Catapult AI NN – From AI/ML Framework to Optimized RTL

(12 mins, 47 secs)

Signature IP: Validating a Scalable PCIe Gen6 Controller Subsystem on Veloce proFPGA

(17 mins, 9 secs)

Calibre: Design Solutions Roadmap at DAC 2024

(14 mins, 39 secs)

ST: How AI and Advanced Verification can Help Accelerate .lib Characterization And Analysis To Ensure High Quality SOCs

(21 mins, 47 secs)

Micron: How Solido’s AI Assisted Design Optimization Handles Extensive Design Spaces

(16 mins, 12 secs)

Siemens Workflow For Intel Foundry EMIB Heterogeneous Integration Platform

(14 mins, 56 secs)

Amazon Web Services: Harnessing the Power of AWS Cloud to Scale Siemens EDA Offerings for Chip Designs

(16 mins, 16 secs)

SiFive: Accelerating the Path to Quality and Performance in RISC-V Processors with FPGA Technology

(15 mins, 29 secs)

Accelerated Confidence in Interface Designs Mixing Software Layers, Hardware Protocols, Physical Connections

(18 mins, 18 secs)

Calibre 3DThermal 3DIC Feasibility Analysis to Final Sign Off Solution

(17 mins, 41 secs)

SOC Verification Using VirtuaLab

(13 mins, 33 secs)

Designing for Low-Power? Glitches Can Ruin your Day!

(7 mins, 17 secs)

Introducing Smart Verification: Unleashing the Potential of AI Within Functional Verification

(30 mins, 56 secs)

Taking 3DIC Heterogeneous Integration Mainstream

(25 mins, 46 secs)

Veloce System Interconnect (VSI): Comprehensive Framework for Creation of Digital Twins

(23 mins, 37 secs)