Siemens EDA at Chiplet Summit
Feb. 17-19, 2026 | Santa Clara, CA
Visit us at Booth #200. See live end-to-end workflow demos and hear from Intel, Fraunhofer, Arm experts, and discuss 2026 priorities with our team.
Keynote sponsor
Don't miss our keynote
Feb. 18 | 11:30 a.m. - Noon
Redefine 3D IC performance for AI — with AI
Hear Juan Rey, VP & GM of Calibre / Siemens EDA CTO, on AI's role in three-dimensional integrated circuit (3D IC) design strategies.
Redefine 3D IC development cycle at booth #200
Explore the Siemens unified 3D IC workflow in action. Unlock faster and more power, performance and area (PPA) convergence.
Unified, AI-driven 3D IC solutions
Discover how Siemens unified, AI-driven 3D IC solutions integrate planning, analysis, signoff and testing to deliver true system technology co-optimization (STCO).
Predictive multiphysics analysis
Explore integrated thermal, mechanical and electrical modeling from die to system levels to identify reliability risks early.
Holistic UCIe-based flow
Explore the complete 64G UCIe design flow featuring Alphawave Semi’s IP and Siemens' integrated design tools from pre-layout analysis through final signoff.
Expert theatre sessions
- 12:45pm - 1:00pm - System Co-Design Considerations for 64G UCIe Interconnects
Archana Cheruliyil | Principal Product Marketing Manager | Alphawave Semi - 1:30pm - 1:45pm - Chipletz Advanced Packaging Solution
Jeff Cain | VP of Engineering | Chipletz - 2:15pm - 2:30pm
Satish Surana | Senior Principal Engineer | Intel - 3:00pm - 3:15pm - Foundry 2.0
Bob Patti | President/CEO | NHanced Semiconductors - 3:45pm - 4:00pm
Andy Heinig | Head of Department Efficient Electronics | Fraunhofer - 4:30pm - 4:45pm - Redesigning Chip Design with Generative and Agentic AI using Fuse EDA AI System
Niranjan Sitapure | Central AI Product Manager | Siemens EDA - 5:15pm - 5:30pm - Unifying Silicon, Package, and System Data for 3D IC Design
Vishal Moondhra | VP, Solutions Engineering | Perforce & Michael Munsey | VP Semiconductor Industry | Siemens EDA - 6:00pm - 6:15pm - TCG-Aligned Chiplet Security via Standardized DFT Interfaces
Ranga Desikachari | Director of Engineering | Crypto Quantique
- 12:15pm - 12:30pm - ATD Shift-left for SoC Verification: Accelerating the chiplet ecosystem
Karthik Padmakumar | ARM - 1:00pm - 1:15pm - Identity-Centric Security: Bridging Hardware Root of Trust to Scalable Chiplet Lifecycle Management
Chris Jones | Director of Applications | Crypto Quantique
Siemens EDA papers and presentations
- A-101: Security | 2:30 p.m. - 3:30 p.m. | GAMR 1
Scalable Chiplet Integration with UCIe 3.0 and RoT
Luis Li Chang | Senior Software Engineer | Siemens EDA
Leveraging DFT Architectures to Enable Chiplet Security
Lee Harrison | Director, Automotive IC Solutions | Siemens EDA - B-101: Die-to-Die Interfaces - 1: Advanced Technology | 2:30 p.m. - 3:30 p.m. | GAMR 2
Applying AI and Automation to UCIe Multi-Die Systems
Prashant Dixit | Architect | Siemens EDA & Ujjwal Negi | Senior Member Technical Staff | Siemens EDA
Verifying Heterogeneous Accelerator Designs Based on UALink
Justin Bunnell | Technical Product Manager | Siemens EDA - G-101: Forum on Digital Twins for Chiplets | 2:30 p.m. - 3:30 p.m. | Room 209
Shorten Chiplet Development Time by Using Digital Twins
Michael Munsey | Vice President Semiconductor & Electronics | Siemens EDA - A-102: Design - 1 | 3:45 p.m. - 4:45 p.m. | GAMR 1
Thermal Aware Chiplet and Power Pins Floorplanning
Andras Vass-Varnai | 3D IC Mechanical Reliability Solutions Engineer | Siemens EDA - B-102: Die-to-Die Interfaces - 2: Advanced Packaging | 3:45 p.m. - 4:45 p.m. | GAMR 2
UCIe Channel Compliance Simulation: Substrate/Interposer Design Tradeoffs
John Caka | Field Application Engineer | Siemens EDA - A-103: STCO/AI | 5:00 p.m. - 6:20 p.m. | GAMR 1
Digital Twin-Based Approach to 3D IC Designs Using STCO
Pratyush Kamal | Director, Central Engineering Solutions | Siemens EDA - B-103: Die-to-Die Interfaces - 3: Technical Issues | 5:00 p.m. - 6:00 p.m. | GAMR 2
Tackling Electrical Complexity in UCIe
Luis E. Rodriguez | Technical Product Manager | Siemens EDA & Jonathan Ramirez | UCIe Verification Engineer | Siemens EDA - E-103: Advanced Packaging Solutions | 5:00 p.m. - 6:20 p.m. | Room 203
Chip/Package Co-Design (CPO): Enabling the Path to I/O Density and Efficiency
Anthony Mastroianni | Senior Director 3DIC Solutions Engineering | Siemens EDA - H-103: Design - 3 | 5:00 p.m. - 6:20 p.m. | Room 210
Extending Thermal Simulation to 3D IC Systems
Subarmanian Lalgudi | Multi-physics Solutions Architect | Siemens EDA
- A-201: Design - 4 | 9:00am - 10:00am | GAMR 1
Engineering Resilient IC Packages
Sudarshan Deo | Software Engineering Manager, 3D IC R&D | Siemens EDA & Andras Vass-Varnai | 3D IC Mechanical Reliability Solutions Engineer | Siemens EDA - F-201: Die-to-Die Interfaces - 5: High-Frequency Applications | 9:00am - 10:00am | Room 201
Comprehensive Verification of UCIe Management Systems
Prashant Dixit | Architect | Siemens EDA & Ujjwal Negi | Senior Member Technical Staff | Siemens EDA - A-202: Testing | 3:00pm - 4:20pm | GAMR 1
Die-to-Die Interconnect Defect Modeling and Repair Architecture
Moiz Khan | Principal Engineer | Siemens EDA, Anshuman Chandra | Principal Engineer | Siemens EDA & Jonathan Gaudet | Senior Engineering Manager | Siemens EDA
A consistent In-System Design-for-Test Architecture for 3D Devices
Martin Keim | Senior Engineering Director | Siemens EDA - F-202: Die-to-Die Interfaces - 7: Other Stages | 3:00pm - 4:20pm | Room 204
Scaling Chiplet Verification
Karim Ameziane | Head of Product Engineering, Simulation and Debug Product Line | Siemens EDA - A-203: Reducing Overall Test Costs | 4:30pm - 5:50pm | GAMR 1
Enabling Advanced Transceiver Verification for Chiplet Architectures
Lih-Jen Hou | Senior Technical Product Manager | Siemens EDA & Scott Wedge | Director, R&D | Siemens EDA
More info and Register
Want to see the full agenda, see travel details or register? We look forward to connecting with you at Chiplet Summit.