{"breadcrumbs":[],"image":"https://images.sw.cdn.siemens.com/siemens-disw-assets/public/3NBWhuCWodESoym5ln1ew3/en-US/U2U_Banner_E-M_0421V4.jpg?w=1920&q=60","logo":"//images.ctfassets.net/17si5cpawjzf/3y80vnJEmKyNOuLpN0mwiz/e4718c74aaca3b2e58bce0d052f6cfba/Trimmed_RealizeLIVE_U2U_Logo.png","logo_alt":"RealizeLive and U2U 2021","primaryButton":{"text":"Save your Seat: 5–5:45AM PDT","url":"https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/536183"},"secondaryButton":{"text":"Save your Seat: 9:45–10:30AM PDT","url":"https://events.sw.siemens.com/en-US/realizelive/agenda?agendaPath=session/536206"},"rotatingText":["fact","fiction"],"staticTextStart":"C++ to RTL with HLS @ push of a button -","staticTextEnd":"?","overlay":false,"height":400,"description":""}
C++ to RTL with HLS @ push of a button - fact ?
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Siemens EDA Experience

High-Level Synthesis & <br> RTL Low-Power

<p>High-Level Synthesis (HLS) is hot in markets like Deep Learning/AI, Computer Vision, Communication (5G, IoT), and Video, just to name a few, and designing at the C-level with a fast path and the highest QofR (performance, area, and power) for both FPGA and ASIC implementation brings a competitive differentiation and accelerated time-to-market. Having a complete low-power methodology from block to SoC whether starting from C or RTL is also critical in emerging ultra-power sensitive markets. This year at Realize LIVE + U2U, Siemens EDA technical experts, customers, and researchers present the latest methodologies and discuss their success using the complete solution of Siemens&#39; Implementation tools: the Catapult® Platform for both HLS and High-Level Verification (HLV) and the PowerPro® Platform for power metrics, analysis, and optimization.</p>
MUST WATCH SESSIONS!

Expert Speakers @ Realize LIVE + U2U 2021

Explore the High-Level Synthesis and RTL Low-Power Experience at Realize LIVE + U2U 2021.

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ONDEMAND TRAINING

Catapult High-Level Synthesis & Verification Library

<p>Join the thousands of hardware designers learning about Catapult HLS - the biggest industry disruption in silicon design in last 20 years with a 30-day free trial! Catapult®&#39;s On-Demand Training Library can help you discover how Catapult can be used to create optimized RTL faster and easier. This complementary offer includes technical videos and virtual labs from the complete Catapult On-Demand Training Library.</p>

VIDEO SERIES

Designing ML Hardware Accelerators Using HLS

<p>The following video series provides an introduction into designing simple ML accelerators using HLS. </p>

VIDEO SERIES

Edge Detection Walkthrough Video Series

<p>This 9-part video series provides a step-by-step walkthrough of what is needed to take a C++ floating-point algorithm all the way to optimized RTL using Catapult High-Level Synthesis.</br></p>

CONNECT SESSION

C++ to RTL with HLS at the Push of a Button

<p>HLS Technologist and 15-year HLS veteran/HW designer, Mike Fingeroff, will explore some of the most commonly asked questions and statements to separate fact from fiction and talk about where HLS is today. The interactive format will give you the chance to join the conversation, stump the experts with your questions, or simply listen and learn. Save your seat for this exclusive live session on May 26!</p>

EDA INSIGHTS WITH JOE SAWICKI

Silicon to Systems: from Vision to Reality

<p>Semiconductor innovation is fueling digitalization as SoCs become ever more complex hardware and software systems. To thrive requires a visionary approach, in a semiconductor industry primed to surpass a trillion dollars in revenue by 2030. Joe Sawicki, EVP IC, Siemens EDA, shares how three tenets of technology, design, and system scaling, on a foundation of AI, help you engineer a smarter future faster.</br></br> </p>

PORTFOLIO

Xcelerator – Embrace the Digital Future

<p>Our comprehensive and integrated portfolio of software and services for electronic and mechanical design, system simulation, manufacturing, operations and lifecycle analytics.</p>

Xcelerator