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June 13 - 14, 2023

Visit Siemens at PCI-SIG Developers Conference 2023

Siemens EDA offers a variety of ways to engage with our PCIe® experts at the upcoming PCI-SIG DevCon in Santa Clara, CA. Siemens will showcase our field-proven PCIe® 6 verification IP as well as simulation and emulation approaches for PCIe® verification.

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PCI-SIG is committed to the development and enhancement of the PCI standard. Crediting its success to the contribution of over 800 members, PCI-SIG strives to provide them with the resources needed to remain competitive.

Scheduled Meetings

Request a scheduled meeting while at PCI-SIG, or drop in to visit us in booth 16.

Siemens EDA Demos: Verification IP for PCIe® 6

  • Visit Siemens EDA in booth 16 for a demonstration of Siemens mature and field-proven verification IP and test suites for PCIe® 6.
Member Implementation Showcases

Join Siemens EDA PCIe® experts

Wednesday, 10:30 AM | Tufail Ansari

Implementing AES-GCM for PCIe® IDE

This presentation demonstrates how the MAC can be computed and encrypted, data can be generated parallelly and efficiently over multiple aggregated TLPs, and how buffering of TLPs can be avoided at transmitter.

Wednesday, 11:30 AM | Richa Gupta

IDE Verification and its Challenges

This presentation explains the requirements, verification scenarios, and challenges for IDE.

Additional Resources

Available PCIe® Gen 6 Webinars

Learn from the industry experts by viewing the latest Verification IP updates.

With shared flow control there is a common buffer space pool that can be used by traffic directed to any enabled VC that contributed to that shared pool, irrespective of TC-VC mapping, consequently increasing the throughput of the link.
Cost-effective and scalable
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Effective resource utilization in PCIe Gen6

All shared resources of every active VC form a combined, shared pool that can be used per the requirement. If individual buffer space is exhausted, more traffic can be received if resources are available in the common shared pool.

CXL and IDE
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Protecting High Speed Interconnects

ON-DEMAND WEBINAR

Rambus & Siemens discuss the background of IDE, threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Learn how to incorporate and validate this essential standard in your designs.

View on-demand recording.
QVIP Configurator JumpStart
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A Guide to QVIP Workflow and Debug for PCIe®

ON-DEMAND WEBINAR

This session walks through the step-by-step workflow to integrate Questa Verification IP (QVIP) - PCIe® into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP.

What is PCIE® 6.0?
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Preparing for PCIe® Gen 6

ON-DEMAND WEBINAR

PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

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Verification Academy

Verification Academy provides the skills necessary to mature an organization's functional verification process capabilities, providing a methodological bridge between high-level value propositions and the low-level details.

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Verification Horizons blog

Insight and updates on concepts, values, standards, methodologies, and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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Verification Horizons

The Verification Horizons publication provides concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them.

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