Osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees. As such, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product roadmap.
Topic | Presenter |
---|---|
Limits of verification: learnings from catastrophic system failures | Philippe Luc - Codasip |
Spectres, Meltdowns, Zombies, Orcs: How formal methods could banish the ghosts that haunt our computing systems | Prof. Wolfgang Kunz - RPTU |
How to sign-off cryptographic hash implementations with generated formal assertions | Tobias Ludwig - Lubis EDA |
Debugging enhancements for formal property checking | Holger Busch - Infineon |
Lunch | < All > |
Reducing formal verification runtime in SystemC utilizing modular interface | Hideki Kazama - Sony |
Hierarchical verification flow for FPGA design projects | Mamma Benmoussa Garsault - Arcys |
Safeguarding datapath integrity and compliance with formal security verification | Keerthi Devarajegowda - Siemens |
Combined formal and functional verification approach for digitally controlled analog frontend | Mihajlo Katona - Veriest |
Formal technology update and roadmap | Chris Giles, Siemens |
If you have any questions, email osmosis.sisw@siemens.com with the "osmosis” keyword in the subject header.
It was great to see everyone!!!
The Siemens Formal Verification Team