Osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees. As such, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product roadmaps.
Check-in and continental breakfast - doors open at 8:00 AM, Program starts at 9:00 AM
Start | Topic | Presenter |
---|---|---|
9:00AM | The state of functional verification: Crisis or opportunity? | Harry Foster, Siemens |
9:45AM | Make formal simple and easy-to-use with generated Assertion IP | Tobias Ludwig, Lubis EDA |
10:15AM | The X-factors of X-checking | Kanthi Palaniappan, Nokia; Neil Rattray, Siemens |
10:45AM | Formal coverage: an approach to analyze property holes | Aishwarya Sridhar & Paritosh Kumar, Infineon; Pallavi Atha, Siemens |
11:15AM | How formal lights up your RISC-V verification avenue | Philippe Luc, Codasip |
11:45AM | Accelerator quick error detection: Verification of hardware accelerators | Saranyu Chattopadhyay, Stanford University |
12:15PM | Lunch - Restaurant Grat | |
13:30PM | Exhaustive trust & security verification by | John Hallman, Siemens |
14:00PM | Crossing the RISC-V customization barrier with formal | Pascal Gouedo, Dolphin Design |
14:30PM | A novel approach to formal FW/HW co-verification | Djones Lettnin, Infineon; Jörg Bormann, Siemens |
15:00PM | Coffee Break, Lobby | |
15:30PM | UPEC: Side Channel Detection with Formal Verification | Keerthi Devraj, Siemens |
16:00PM | EC-FPGA updates with an introduction to Instance Mapping | Kevin Urish, Siemens |
16:30PM | Formal verification of high consequence systems | Ratish Punnoose, Sandia National Lab |
17:00PM | Product plans and roadmap update: formal for the next normal | Chris Giles, Siemens |
If you have any questions (including whether if you could “bump” one of our R&D presenters to share your formal verification story), email osmosis.sisw@siemens.com with the "osmosis” keyword in the subject header.
We look forward to seeing you!!!
The Siemens Formal Verification Team
* The agenda and speakers are subject to change without notice.