Osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees. As such, we have put together the following conference program covering a wide range of formal verification topics – along with delivering sneak-previews of our future product roadmaps.
Check-in and continental breakfast - doors open at 8:00 AM, Program starts at 9:00 AM
The state of functional verification: Crisis or opportunity?
Harry Foster, Siemens
Make formal simple and easy-to-use with generated Assertion IP
Tobias Ludwig, Lubis EDA
The X-factors of X-checking
Kanthi Palaniappan, Nokia; Neil Rattray, Siemens
Formal coverage: an approach to analyze property holes
Aishwarya Sridhar & Paritosh Kumar, Infineon; Pallavi Atha, Siemens
How formal lights up your RISC-V verification avenue
Philippe Luc, Codasip
Accelerator quick error detection: Verification of hardware accelerators
Saranyu Chattopadhyay, Stanford University
Lunch - Restaurant Grat
Exhaustive trust & security verification by
John Hallman, Siemens
Crossing the RISC-V customization barrier with formal
Pascal Gouedo, Dolphin Design
A novel approach to formal FW/HW co-verification
Djones Lettnin, Infineon; Jörg Bormann, Siemens
Coffee Break, Lobby
UPEC: Side Channel Detection with Formal Verification
Keerthi Devraj, Siemens
EC-FPGA updates with an introduction to Instance Mapping
Kevin Urish, Siemens
Formal verification of high consequence systems
Ratish Punnoose, Sandia National Lab
Product plans and roadmap update: formal for the next normal
Chris Giles, Siemens
If you have any questions (including whether if you could “bump” one of our R&D presenters to share your formal verification story), email firstname.lastname@example.org with the "osmosis” keyword in the subject header.
We look forward to seeing you!!!
The Siemens Formal Verification Team
* The agenda and speakers are subject to change without notice.